公开(公告)号：US20220157875A1

公开(公告)日：2022-05-19

申请号：US17097360

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Sheng-Chau Chen ,  Hsun-Chung Kuang ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

公开(公告)号：US11189654B2

公开(公告)日：2021-11-30

申请号：US16900985

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Chia-Hsing Chou ,  Yi-Ming Lin ,  Min-Hui Lin ,  Chin-Szu Lee

IPC: H01L21/02 ,  H01L27/146 ,  H01L21/762

Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

公开(公告)号：US20210225919A1

公开(公告)日：2021-07-22

申请号：US17219960

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Keng-Yu Chou ,  Yeur-Luen Tu

IPC: H01L27/146

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.

公开(公告)号：US20200006145A1

公开(公告)日：2020-01-02

申请号：US16178819

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US20190067355A1

公开(公告)日：2019-02-28

申请号：US15688077

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Keng-Yu Chou ,  Yeur-Luen Tu

IPC: H01L27/146

Abstract: The present disclosure relates to an image sensor integrated chip having a deep trench isolation (DTI) structure having a reflective element. In some embodiments, the image sensor integrated chip includes an image sensing element arranged within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element and one or more absorption enhancement layers are arranged over and between the plurality of protrusions. A plurality of DTI structures are arranged within trenches disposed on opposing sides of the image sensing element and extend from the first side of the substrate to within the substrate. The plurality of DTI structures respectively include a reflective element having one or more reflective regions configured to reflect electromagnetic radiation. By reflecting electromagnetic radiation using the reflective elements, cross-talk between adjacent pixel regions is reduced, thereby improving performance of the image sensor integrated chip.

公开(公告)号：US20180047682A1

公开(公告)日：2018-02-15

申请号：US15236526

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Wen-Jen Tsai ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Yi-Ming Lin ,  Min-Hui Lin

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/02107 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80001 ,  H01L2224/80895 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

公开(公告)号：US20170301709A1

公开(公告)日：2017-10-19

申请号：US15635673

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

公开(公告)号：US11908878B2

公开(公告)日：2024-02-20

申请号：US17327996

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1464 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

公开(公告)号：US20200321251A1

公开(公告)日：2020-10-08

申请号：US16908966

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US20200075657A1

公开(公告)日：2020-03-05

申请号：US16121958

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.