公开(公告)号：US11676855B2

公开(公告)日：2023-06-13

申请号：US17094700

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/027 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20

CPC classification number: H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US20240363353A1

公开(公告)日：2024-10-31

申请号：US18449443

申请日：2023-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Yu-Chen Ko ,  Chi-Yuan Chen ,  Ya-Yi Cheng ,  Chun-I Tsai ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

公开(公告)号：US20210257255A1

公开(公告)日：2021-08-19

申请号：US17227831

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Tz-Shian Chen ,  Cheng-Jung Sung ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

公开(公告)号：US10998269B2

公开(公告)日：2021-05-04

申请号：US16908113

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US20190267211A1

公开(公告)日：2019-08-29

申请号：US16177530

申请日：2018-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01J37/32 ,  H01L21/02

Abstract: Embodiments described herein relate to plasma processes. A tool includes a pedestal. The pedestal is configured to support a semiconductor substrate. The tool includes a bias source. The bias source is electrically coupled to the pedestal. The bias source is operable to bias the pedestal with a direct current (DC) voltage. The tool includes a plasma generator. The plasma generator is operable to generate a plasma remote from the pedestal. A method for semiconductor processing includes performing a plasma process on a substrate in a tool. The plasma process includes flowing a gas into the tool. The plasma process includes biasing a pedestal that supports the substrate in the tool. The plasma process includes igniting a plasma in the tool using the gas.

公开(公告)号：US20170084485A1

公开(公告)日：2017-03-23

申请号：US15370016

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.

公开(公告)号：US09564398B2

公开(公告)日：2017-02-07

申请号：US13832195

申请日：2013-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Mingh-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/288 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract translation: 描述了具有改进的金属结构的半导体结构。 半导体结构可以包括具有上表面的衬底，在上表面上的互连层，以及沉积在互连层上的附加结构。 互连层可以包括衬底上的图案化种子层，种子层上的至少两条金属线以及相邻金属线之间的电介质材料。 阻挡层可沉积在至少两条金属线上。 还描述了制造半导体结构的方法。

公开(公告)号：US20240332068A1

公开(公告)日：2024-10-03

申请号：US18738256

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US20240274555A1

公开(公告)日：2024-08-15

申请号：US18313746

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Ming-Hsing Tsai ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Kevin Huang ,  Kuan-Hung Ho

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/0239 ,  H01L2224/0384 ,  H01L2224/05073 ,  H01L2224/05184 ,  H01L2224/05582

Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

公开(公告)号：US12033890B2

公开(公告)日：2024-07-09

申请号：US18309131

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.