公开(公告)号：US20220336393A1

公开(公告)日：2022-10-20

申请号：US17361924

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

公开(公告)号：US11362064B2

公开(公告)日：2022-06-14

申请号：US16737856

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

公开(公告)号：US20210335722A1

公开(公告)日：2021-10-28

申请号：US17006365

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/74

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

公开(公告)号：US11107680B2

公开(公告)日：2021-08-31

申请号：US15884328

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu ,  Ying-Ju Chen

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/027 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/10

Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

公开(公告)号：US20210159224A1

公开(公告)日：2021-05-27

申请号：US16697797

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L49/02 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.

公开(公告)号：US20210035953A1

公开(公告)日：2021-02-04

申请号：US17073888

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US09978704B2

公开(公告)日：2018-05-22

申请号：US15255259

申请日：2016-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC: H01L23/00

CPC classification number: H01L24/14 ,  G06F2217/40 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1405 ,  H01L2224/14133 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.

公开(公告)号：US20240395751A1

公开(公告)日：2024-11-28

申请号：US18788526

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

公开(公告)号：US20240290823A1

公开(公告)日：2024-08-29

申请号：US18654658

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01G4/30 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US20240021554A1

公开(公告)日：2024-01-18

申请号：US18356538

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L21/565 ,  H01L24/80 ,  H01L25/50 ,  H01L25/0652 ,  H01L2924/1434 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06586 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.