公开(公告)号：US09653471B2

公开(公告)日：2017-05-16

申请号：US15143811

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/08

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20150295172A1

公开(公告)日：2015-10-15

申请号：US14252111

申请日：2014-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Yu-Hsing Chang ,  Ru-Liang Lee

IPC: H01L45/00 ,  H01L23/538

CPC classification number: H01L45/1253 ,  H01L23/538 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

Abstract translation: 本公开涉及具有底部电极的电阻随机存取存储器（RRAM）单元，其在不使用绝缘侧壁间隔件的情况下提供RRAM单元内的低泄漏电流，以及相关联的形成方法。 在一些实施例中，RRAM单元具有设置在由下层电介质（ILD）层围绕的下金属互连层上的底电极。 底部电介质层设置在下部金属互连层和/或下部ILD层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 将电介质数据存储层放置在底部电介质层上增加了底部和顶部电极之间的泄漏路径距离，从而为RRAM单元提供了低泄漏电流。

公开(公告)号：US11682692B2

公开(公告)日：2023-06-20

申请号：US16871257

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hua Lin ,  Hsun-Chung Kuang ,  Yu-Hsing Chang ,  Yao-Wen Chang

IPC: H01L27/15 ,  H01L33/60 ,  H01L33/40 ,  H01L33/62

CPC classification number: H01L27/156 ,  H01L33/405 ,  H01L33/60 ,  H01L33/62 ,  H01L2933/0066

Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

公开(公告)号：US20210273167A1

公开(公告)日：2021-09-02

申请号：US16806064

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chia-Shiung Tsai ,  Xin-Hua Huang ,  Yu-Hsing Chang ,  Yeong-Jyh Lin

IPC: H01L51/00 ,  H01L51/50 ,  H01L51/56 ,  C23C16/458 ,  C23C16/04

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

公开(公告)号：US20160247812A1

公开(公告)日：2016-08-25

申请号：US15143811

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US09425044B2

公开(公告)日：2016-08-23

申请号：US14461565

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

Abstract translation: 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

公开(公告)号：US09356142B2

公开(公告)日：2016-05-31

申请号：US14310277

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US09287279B2

公开(公告)日：2016-03-15

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20150295005A1

公开(公告)日：2015-10-15

申请号：US14253025

申请日：2014-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/146

CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.

Abstract translation: 本公开的一些实施例涉及深沟槽隔离结构。 该深沟槽隔离结构形成在具有上半导体表面的半导体衬底上。 在相对的深沟槽侧壁之间测量的具有深沟槽宽度的深沟槽延伸到半导体衬底的下半导体表面下方。 填充材料形成在深沟槽中，并且电介质衬垫设置在深沟槽的下表面和侧壁上，以将填充材料与半导体衬底分离。 浅沟槽区域具有从深沟槽的侧壁向上延伸到上半导体表面的侧壁。 浅沟槽区域具有大于深沟槽宽度的浅沟槽宽度。 电介质材料填充浅沟槽区域并在深沟槽中延伸到导电材料的顶部。

公开(公告)号：US11361971B2

公开(公告)日：2022-06-14

申请号：US17032362

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L21/3065 ,  H01L21/308 ,  H01L49/02

Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.