公开(公告)号：US20160172303A1

公开(公告)日：2016-06-16

申请号：US15047809

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Tain-Shang Chang ,  Chia-Han Lai ,  Ren-Hau Yu ,  Ching-Yao Sun ,  Yu-Sheng Wang

IPC: H01L23/532

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole.

公开(公告)号：US20240304725A1

公开(公告)日：2024-09-12

申请号：US18669624

申请日：2024-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US11961768B2

公开(公告)日：2024-04-16

申请号：US18312647

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US20210296450A1

公开(公告)日：2021-09-23

申请号：US17340802

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Ching-Hwanq Su

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

公开(公告)号：US20200343087A1

公开(公告)日：2020-10-29

申请号：US16927638

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Lin ,  Chen-Yuan Kao ,  Rueijer Lin ,  Yu-Sheng Wang ,  I-Li Chen ,  Hong-Ming Wu

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US09449922B2

公开(公告)日：2016-09-20

申请号：US15047809

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Tain-Shang Chang ,  Chia-Han Lai ,  Ren-Hau Yu ,  Ching-Yao Sun ,  Yu-Sheng Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole.

Abstract translation: 在半导体器件的制造方法中，在基板上形成电介质层，并且从电介质层向基板形成接触孔。 介电隔离衬垫被形成以覆盖接触孔的侧壁和底部。 去除介电隔离衬垫的一部分以露出衬底的一部分。 通过接触孔将金属硅化物层形成到衬底中。

公开(公告)号：US09299607B2

公开(公告)日：2016-03-29

申请号：US14179671

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Tain-Shang Chang ,  Chia-Han Lai ,  Ren-Hau Yu ,  Ching-Yao Sun ,  Yu-Sheng Wang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole.

公开(公告)号：US12068197B2

公开(公告)日：2024-08-20

申请号：US17234136

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US11682589B2

公开(公告)日：2023-06-20

申请号：US17068041

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US11670690B2

公开(公告)日：2023-06-06

申请号：US16926671

申请日：2020-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Kei-Wei Chen ,  Yu-Sheng Wang ,  Ming-Ching Chung ,  Chia-Yang Wu

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/49

CPC classification number: H01L29/41725 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/4966

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.