公开(公告)号：US20240126703A1

公开(公告)日：2024-04-18

申请号：US18389899

申请日：2023-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph Raymond Michael ZBICIAK ,  Kai CHIRCA ,  Daniel Brad WU

IPC: G06F12/1027 ,  G06F9/46 ,  G06F9/48 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  H03M13/15

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F9/4881 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  H03M13/1575 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

公开(公告)号：US20240036876A1

公开(公告)日：2024-02-01

申请号：US18487186

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3838

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20240036867A1

公开(公告)日：2024-02-01

申请号：US18378207

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/3802 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30036 ,  G06F9/3867 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F9/30098 ,  G06F11/1048 ,  G06F9/383 ,  G06F9/30112 ,  G06F9/345 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/30101 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/60 ,  G06F2212/452 ,  G06F12/0811

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US20220113966A1

公开(公告)日：2022-04-14

申请号：US17557162

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897

Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

公开(公告)号：US20210294639A1

公开(公告)日：2021-09-23

申请号：US17340211

申请日：2021-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc BUI ,  Timothy D. ANDERSON

IPC: G06F9/48 ,  G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

公开(公告)号：US20190243647A1

公开(公告)日：2019-08-08

申请号：US16384434

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US20180293199A1

公开(公告)日：2018-10-11

申请号：US15903183

申请日：2018-02-23

Applicant: Texas Instruments Incorporated

Inventor： David M. THOMPSON ,  Timothy D. ANDERSON ,  Joseph R. M. ZBICIAK ,  Abhijeet A. CHACHAD ,  Kai CHIRCA ,  Matthew D. PIERSON

IPC: G06F13/40 ,  G06F13/42 ,  H04L12/801 ,  G06F13/364 ,  H04L12/819

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US20230350681A1

公开(公告)日：2023-11-02

申请号：US18344984

申请日：2023-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F9/345 ,  G06F12/0875 ,  G06F11/00 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US20220365787A1

公开(公告)日：2022-11-17

申请号：US17876706

申请日：2022-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Timothy D. ANDERSON ,  Paul Daniel GAUVREAU

IPC: G06F9/38 ,  G06F9/54 ,  G06F11/36 ,  G06F9/30 ,  G06F9/48

Abstract: A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.

公开(公告)号：US20210247980A1

公开(公告)日：2021-08-12

申请号：US17241198

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.