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公开(公告)号：US08043958B1
公开(公告)日：2011-10-25
申请号：US12875857
申请日：2010-09-03
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。
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公开(公告)号：US07967969B2
公开(公告)日：2011-06-28
申请号：US12578310
申请日：2009-10-13
申请人： Steven T. Mayer , Jonathan D. Reid
发明人： Steven T. Mayer , Jonathan D. Reid
CPC分类号： C25D17/12 , C25D7/123 , C25D17/001 , C25D17/008 , H01L21/2885 , Y10S204/07
摘要： A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.
摘要翻译： 将基本上均匀的金属层电镀在其上具有种子层的工件上。 这是通过使用“高电阻离子电流源”来实现的，其通过将高电阻膜（例如，微孔陶瓷或微波玻璃元件）放置在靠近晶片来解决端子问题，从而消除系统的电阻。 因此，膜近似于恒定电流源。 通过保持晶片靠近膜表面，从膜顶部到表面的离子电阻远小于对晶片边缘的离子路径电阻，基本上补偿薄金属膜中的薄层电阻并引导附加电流 在晶片的中心和中间。
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公开(公告)号：US07811925B1
公开(公告)日：2010-10-12
申请号：US12184145
申请日：2008-07-31
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。
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公开(公告)号：US07449098B1
公开(公告)日：2008-11-11
申请号：US10739822
申请日：2003-12-17
申请人： Steven T. Mayer , Jonathan D. Reid , Mark L. Rea , Ismail T. Emesh , Henner W. Meinhold , John S. Drewery
发明人： Steven T. Mayer , Jonathan D. Reid , Mark L. Rea , Ismail T. Emesh , Henner W. Meinhold , John S. Drewery
CPC分类号： B23H5/08 , C25D5/06 , C25D5/22 , C25D5/34 , C25D5/48 , C25D7/123 , C25F3/16 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76877
摘要： A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.
摘要翻译： 一种公开的机械辅助电镀形式导致平坦，薄的覆盖层。 在一个实例中，加速器沉积在铜表面上并在简化的类似CMP的装置中机械地去除。 然后将晶片镀在含有很少或没有加速添加剂的电解质中。
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公开(公告)号：US06890416B1
公开(公告)日：2005-05-10
申请号：US10318497
申请日：2002-12-11
摘要： An electroplating apparatus prevents anode-mediated degradation of electrolyte additives by creating a mechanism for maintaining separate anolyte and catholyte and preventing mixing thereof within a plating chamber. The separation is accomplished by interposing a porous chemical transport barrier between the anode and cathode. The transport barrier limits the chemical transport (via diffusion and/or convection) of all species but allows migration of ionic species (and hence passage of current) during application of sufficiently large electric fields within electrolyte.
摘要翻译： 电镀装置通过产生用于维持单独的阳极电解液和阴极电解液并防止其在电镀室内的混合的机构来防止阳极介导的电解质添加剂的降解。 分离是通过在阳极和阴极之间插入多孔化学传输屏障来实现的。 运输屏障限制了所有物种的化学传输（通过扩散和/或对流），但是在电解质中施加足够大的电场期间允许离子物质的迁移（因此电流的流动）。
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16.发明授权Method and apparatus for uniform electroplating of thin metal seeded wafers using multiple segmented virtual anode sources 有权使用多分段虚拟阳极源均匀电镀薄金属晶种晶片的方法和装置公开(公告)号：US06773571B1
公开(公告)日：2004-08-10
申请号：US10154082
申请日：2002-05-22
申请人： Steven T. Mayer , Evan E. Patton , Brian Paul Blackman , Jonathan D. Reid , Thomas Anand Ponnuswamy , Harold D. Perry
发明人： Steven T. Mayer , Evan E. Patton , Brian Paul Blackman , Jonathan D. Reid , Thomas Anand Ponnuswamy , Harold D. Perry
IPC分类号： C25D500
CPC分类号： C25D7/123 , C25D17/001 , C25D17/12
摘要： The present invention pertains to methods and apparatus for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. The total current of a plating cell is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte to compensate for resistance and voltage variation across a work piece due to the seed layer. Focusing elements are used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.
摘要翻译： 本发明涉及用于将基本上均匀的金属层电镀到其上具有种子层的工件上的方法和装置。 电镀单元的总电流分布在电镀单元中的多个阳极之间，以便调整电镀电解质中的电流分布，以补偿因种子层而导致的工件上的电阻和电压变化。 聚焦元件用于在工件的电镀表面附近创建“虚拟阳极”，以进一步控制电镀期间电解液中的电流分布。
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公开(公告)号：US06551487B1
公开(公告)日：2003-04-22
申请号：US09872341
申请日：2001-05-31
申请人： Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind
发明人： Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind
IPC分类号： C25D500
CPC分类号： H01L21/2885 , C25D17/001 , Y10S414/135 , Y10S414/136
摘要： The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.
摘要翻译： 在电镀过程中控制晶片相对于电解质表面的取向。 将晶片沿着垂直于电解质表面的轨迹输送到电解质浴中。 沿着该轨迹，晶片在进入电解质之前是成角度的，用于倾斜的浸入。 根据给定情况下的最佳选择，晶圆可以以倾斜的方向进行电镀。 此外，在一些设计中，晶片的取向可以在浸入期间或在电镀期间被主动调节，从而在各种电镀场景中提供灵活性。
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公开(公告)号：US20120181170A1
公开(公告)日：2012-07-19
申请号：US13432767
申请日：2012-03-28
申请人： Vinay Prabhakar , Bryan L. Buckalew , Kousik Ganesan , Shantinath Ghongadi , Zhian He , Steven T. Mayer , Robert Rash , Jonathan D. Reid , Yuichi Takada , James R. Zibrida
发明人： Vinay Prabhakar , Bryan L. Buckalew , Kousik Ganesan , Shantinath Ghongadi , Zhian He , Steven T. Mayer , Robert Rash , Jonathan D. Reid , Yuichi Takada , James R. Zibrida
IPC分类号： C25D17/08
CPC分类号： C25D17/001 , C25D7/123
摘要： Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.
摘要翻译： 提供了诸如基板，密封圈和接触环组件的方法，装置和各种装置部件，以减少设备中接触区域的污染。 在电镀工艺之后从设备中取出半导体晶片时可能发生污染。 在某些实施方案中，使用具有疏水涂层的基板，例如聚酰胺 - 酰亚胺（PAI）和有时聚四氟乙烯（PTFE）。 此外，接触环组件的接触尖端可以被定位成更远离唇密封的唇缘。 在某些实施方案中，接触环组件和/或唇膏的一部分还包括疏水性涂层。
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19.发明授权公开(公告)号：US08147660B1
公开(公告)日：2012-04-03
申请号：US11731706
申请日：2007-03-30
申请人： Steven T. Mayer , Jonathan D. Reid
发明人： Steven T. Mayer , Jonathan D. Reid
CPC分类号： C25D17/002 , C25D17/001 , C25D17/005 , C25D17/008 , C25D17/06 , C25D17/10 , C25D17/12 , C25D21/12 , C25F7/00 , H01L21/2885 , H01L21/76877 , Y10S204/07
摘要： A semiconductive counter electrode covers a highly electronically conductive electric current buss. The semiconductive counter electrode is impervious to ion flow. A substrate holder is operable to hold a substrate and to form a thin fluid gap between the semiconductive counter electrode and a substrate surface. A thin liquid electrolyte layer is located in the thin fluid gap. A power supply connected to the electric current buss and a peripheral edge of a conductive substrate surface is able to generate a potential difference between the electric current buss and the semiconductive counter electrode, on one side of the electrolyte layer, and the substrate on the other side. The semiconductive counter electrode provides a substantial resistance in the various current flow paths between the electric current buss and the semiconductive counter electrode, on one side, and the conductive substrate surface, on the other, thereby enhancing control of current distribution.
摘要翻译： 半导体对电极覆盖高度电子导电的电流总线。 半导体对电极不受离子流的影响。 衬底保持器可操作以保持衬底并且在半导体对电极和衬底表面之间形成薄的流体间隙。 薄的液体电解质层位于薄的液体间隙中。 连接到电流母线的电源和导电衬底表面的外围边缘能够在电解质层的一侧上产生电流母线和半导体对电极之间的电位差，并且在另一侧上产生衬底 侧。 半导体对电极在电流总线和半导体对电极之间的一侧和导电基板表面上的各种电流流动路径中提供了显着的电阻，从而增强了电流分布的控制。
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公开(公告)号：US20110083965A1
公开(公告)日：2011-04-14
申请号：US12577619
申请日：2009-10-12
摘要： An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.
摘要翻译： 用于在半导体衬底上填充凹陷特征的电镀设备包括电解质浓缩器，其被配置用于浓缩具有Cu 2+离子的电解质，以形成在20℃下已经过饱和的浓缩电解质溶液。电解质保持在高于 20℃，例如至少约40℃。该设备还包括浓缩电解质储存器和电镀池，其中电镀单元被配置为在至少约40℃的温度下用浓缩电解质电镀。 在至少约40℃的温度下，具有Cu2 +浓度至少约60g / L的电解质的电镀导致非常快的铜沉积速率，并且特别适合于填充大的高纵横比特征，例如通过 硅通孔。
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