公开(公告)号：US20210287936A1

公开(公告)日：2021-09-16

申请号：US17334389

申请日：2021-05-28

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

公开(公告)号：US20210242074A1

公开(公告)日：2021-08-05

申请号：US16782344

申请日：2020-02-05

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Xinghua Sun ,  Angelique Raley

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  H01L21/311

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

公开(公告)号：US10378105B2

公开(公告)日：2019-08-13

申请号：US15610165

申请日：2017-05-31

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Kandabara N. Tapily ,  Takahiro Hakamata ,  Subhadeep Kal ,  Gerrit J. Leusink

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/60 ,  H01L21/205 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3105 ,  C23C16/40 ,  B01D53/76 ,  C23C16/455 ,  C23C16/04

Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.

公开(公告)号：US20190237331A1

公开(公告)日：2019-08-01

申请号：US16252949

申请日：2019-01-21

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Andrew Metz

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

公开(公告)号：US10014213B2

公开(公告)日：2018-07-03

申请号：US15293902

申请日：2016-10-14

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Kandabara N. Tapily ,  Robert D. Clark ,  Gerrit J. Leusink

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76876 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53242

Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.

公开(公告)号：US20170342553A1

公开(公告)日：2017-11-30

申请号：US15610165

申请日：2017-05-31

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Kandabara N. Tapily ,  Takahiro Hakamata ,  Subhadeep Kal ,  Gerrit J. Leusink

IPC: C23C16/40 ,  H01L21/3105 ,  H01L21/205 ,  B01D53/76 ,  C23C16/455 ,  H01L21/31 ,  H01L21/60

CPC classification number: C23C16/40 ,  B01D53/76 ,  B01D2251/202 ,  C23C16/04 ,  C23C16/401 ,  C23C16/455 ,  C23C16/45563 ,  H01L21/02057 ,  H01L21/205 ,  H01L21/28562 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76826 ,  H01L21/76849 ,  H01L2021/60052

Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.

公开(公告)号：US20170241014A1

公开(公告)日：2017-08-24

申请号：US15435970

申请日：2017-02-17

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Gerrit J. Leusink ,  Cory Wajda ,  Tadahiro Ishizaka ,  Takahiro Hakamata

IPC: C23C16/16 ,  C23C16/44 ,  C23C16/455

CPC classification number: C23C16/16 ,  C23C16/4408 ,  C23C16/4481 ,  C23C16/45523 ,  C23C16/45557

Abstract: A method for material deposition is described in several embodiments. According to one embodiment, the method includes providing a substrate defining features to receive a deposition of material, initiating a flow of a Ru carbonyl precursor to the substrate, the Ru carbonyl precursor decomposing within the defined features such that a Ru metal film is deposited on surfaces of the defined features and CO gas is released, and stopping the flow of the Ru carbonyl precursor to the substrate. The method further includes flowing additional CO gas to the substrate after stopping the flow of the Ru carbonyl precursor to the substrate, and repeatedly cycling between process steps of flowing the Ru carbonyl precursor to the substrate and flowing the additional CO gas to the substrate. In one embodiment, the Ru carbonyl precursor contains Ru3(CO)12.

公开(公告)号：US09711449B2

公开(公告)日：2017-07-18

申请号：US15172648

申请日：2016-06-03

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Gerrit J. Leusink ,  Cory Wajda ,  Tadahiro Ishizaka ,  Takahiro Hakamata

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/53242

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

公开(公告)号：US20240087891A1

公开(公告)日：2024-03-14

申请号：US17931838

申请日：2022-09-13

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Shihsheng Chang ,  Kai-Hung Yu ,  Yun Han

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.

公开(公告)号：US11688604B2

公开(公告)日：2023-06-27

申请号：US16582297

申请日：2019-09-25

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Angelique Raley

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.