公开(公告)号：US20160276434A1

公开(公告)日：2016-09-22

申请号：US15166271

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

Abstract translation: 提供半导体器件。 半导体器件包括衬底; 设置在衬底上的第一纳米线; 设置在衬底上的第二纳米线; 形成在第一和第二纳米线的第一端处的第一焊盘，形成在第一和第二纳米线的第二端处的第二焊盘，其中焊盘包括与纳米线不同的材料; 以及围绕第一和第二纳米线的每一个的至少一部分的栅极。

公开(公告)号：US09034705B2

公开(公告)日：2015-05-19

申请号：US13850887

申请日：2013-03-26

Applicant: United Microelectronics Corp.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US08853060B1

公开(公告)日：2014-10-07

申请号：US13902862

申请日：2013-05-27

Applicant: United Microelectronics Corp.

Inventor： Szu-Hao Lai ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Tsai-Yu Wen ,  Hsin-Kuo Hsu

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成凹部。 形成接合层以覆盖凹部的表面。 在接种层上形成缓冲层。 对缓冲层进行蚀刻处理，使缓冲层均匀化并形成。 在均质化的平底形状缓冲层上形成外延层。

公开(公告)号：US11646349B2

公开(公告)日：2023-05-09

申请号：US17511579

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/167

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

公开(公告)号：US20220157814A1

公开(公告)日：2022-05-19

申请号：US17131584

申请日：2020-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Ming-Shiou Hsieh ,  Zih-Hsuan Huang ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.

公开(公告)号：US11195918B1

公开(公告)日：2021-12-07

申请号：US17026062

申请日：2020-09-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

公开(公告)号：US20180108570A1

公开(公告)日：2018-04-19

申请号：US15817274

申请日：2017-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US20180083141A1

公开(公告)日：2018-03-22

申请号：US15823616

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Tsai-Yu Wen ,  Shan Ye ,  Tsuo-Wen Lu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/78391 ,  H01L29/40111 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

公开(公告)号：US20160276431A1

公开(公告)日：2016-09-22

申请号：US14658262

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/161 ,  H01L21/306

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US09431483B1

公开(公告)日：2016-08-30

申请号：US14658262

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。