公开(公告)号：US08741507B1

公开(公告)日：2014-06-03

申请号：US13742361

申请日：2013-01-16

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Ting-Cheng Tseng

IPC: G03F1/70

CPC classification number: G03F1/70

Abstract: A method for separating photomask pattern, including the following steps: first, a layout pattern is provided, wherein the layout pattern is defined to have at least one critical pattern and at least one non-critical pattern. Then, a first split process is performed to separate the critical pattern into a plurality of first patterns and a plurality of second patterns. A second split process is performed to separate the non-critical pattern into a plurality of third patterns and a plurality of fourth patterns. Finally, the first patterns and the third patterns are output to a first photomask, and the second patterns and the fourth patterns are output to a second photomask.

Abstract translation: 一种用于分离光掩模图案的方法，包括以下步骤：首先，提供布局图案，其中布局图案被定义为具有至少一个关键图案和至少一个非关键图案。 然后，执行第一分割处理以将关键图案分离成多个第一图案和多个第二图案。 执行第二分割处理以将非关键图案分离成多个第三图案和多个第四图案。 最后，将第一图案和第三图案输出到第一光掩模，并将第二图案和第四图案输出到第二光掩模。

公开(公告)号：US20140045105A1

公开(公告)日：2014-02-13

申请号：US14065443

申请日：2013-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Huang ,  Ming-Jui Chen ,  Chun-Hsien Huang

IPC: G03F1/76

CPC classification number: G03F1/76 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Abstract translation: 一种用于制造半导体布局的方法包括提供具有多个线图案的第一布局和具有多个连接图案的第二布局，所述多个连接图案定义与线图案中的连接图案重叠的至少第一分割图案， 将第一待分割图案分割成与连接图案重叠的第一待分割图案，分解第一布局以形成第三布局和第四布局，并将第三布局和其他布局输出到 第一掩模和第二掩模。

公开(公告)号：US20240162038A1

公开(公告)日：2024-05-16

申请号：US18167093

申请日：2023-02-10

Applicant: United Microelectronics Corp.

Inventor： Chien Heng Liu ,  Chia-Wei Huang ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L21/027 ,  G03F1/76

CPC classification number: H01L21/0271 ,  G03F1/76

Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.

公开(公告)号：US20230317778A1

公开(公告)日：2023-10-05

申请号：US18206617

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Heng Liu ,  Chia-Wei Huang ,  Hsin-Jen Yu ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

公开(公告)号：US20170221897A1

公开(公告)日：2017-08-03

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US20170162449A1

公开(公告)日：2017-06-08

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/535 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US09653346B2

公开(公告)日：2017-05-16

申请号：US14800697

申请日：2015-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/7851

Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

公开(公告)号：US20170018302A1

公开(公告)日：2017-01-19

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Abstract translation: 静态随机存取存储器单元结构和布局结构包括两个上拉晶体管，两个下拉晶体管，两个槽接触插头和两个金属零互连。 每个金属零互连设置在每个槽接触插头和每个上拉晶体管的栅极上，每个槽接触插塞跨越每个下拉晶体管的漏极和每个上拉晶体管的漏极延伸到 跨越每个金属零互连的一端。 槽接触插塞之间的间隙小于金属零互连之间的间隙。

公开(公告)号：US09208276B1

公开(公告)日：2015-12-08

申请号：US14822907

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

公开(公告)号：US20150036116A1

公开(公告)日：2015-02-05

申请号：US13957436

申请日：2013-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Hsien Hsieh ,  Shih-Ming Kuo ,  Ming-Jui Chen ,  Cheng-Te Wang ,  Jing-Yi Lee

IPC: G03F7/20

CPC classification number: G03F7/70308 ,  G03F7/7025

Abstract: An aperture is configured to be disposed between an illumination source and a semiconductor substrate in a photolithography system. The aperture includes a light-transmission portion with a non-planar thickness profile to compensate the discrepancy of wave-fronts of the light beams of different orders.

Abstract translation: 孔被配置为在光刻系统中设置在照明源和半导体衬底之间。 孔径包括具有非平面厚度轮廓的光透射部分，以补偿不同阶数的光束的波前差异。