公开(公告)号：US20170117410A1

公开(公告)日：2017-04-27

申请号：US14922215

申请日：2015-10-26

Applicant: United Microelectronics Corp.

Inventor： I-cheng Hu ,  Tien-I Wu ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.

公开(公告)号：US09633904B1

公开(公告)日：2017-04-25

申请号：US15352528

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306 ,  H01L29/167 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.

公开(公告)号：US10128366B2

公开(公告)日：2018-11-13

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L29/417 ,  H01L29/165 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180158943A1

公开(公告)日：2018-06-07

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan KU ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu LIN ,  Chun Yao YANG ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/06 ,  H01L21/225 ,  H01L21/768 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US09722030B1

公开(公告)日：2017-08-01

申请号：US15175045

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/165 ,  H01L29/167 ,  H01L23/528 ,  H01L23/532 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20160233092A1

公开(公告)日：2016-08-11

申请号：US14619085

申请日：2015-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Chien-Liang Lin ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28506 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/517

Abstract: A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.

Abstract translation: 门形成工艺包括以下步骤。 在基板上形成栅极电介质层。 在栅介质层上形成阻挡层。 硅晶种层和硅层依次直接形成在阻挡层上，其中硅晶种层和硅层由不同的前体形成。

公开(公告)号：US09397214B1

公开(公告)日：2016-07-19

申请号：US14622943

申请日：2015-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Hsin-Chang Wu ,  Chun-Yu Chen ,  Ming-Hua Chang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Neng-Hui Yang

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/36 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at two sides of the gate structure, and a boron-rich interface layer. The boron-rich interface layer includes a bottom-and-sidewall portion and a top portion, and the epitaxial source/drain structure is enclosed by the bottom-and-sidewall portion and the top portion.

Abstract translation: 提供了一种半导体器件，包括衬底，形成在衬底上的栅极结构，分别形成在栅极结构的两侧的外延源极/漏极结构和富含硼的界面层。 富硼界面层包括底侧和侧壁部分和顶部，并且外延源极/漏极结构被底部和侧壁部分以及顶部部分包围。

公开(公告)号：US20160126091A1

公开(公告)日：2016-05-05

申请号：US14532015

申请日：2014-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chueh-Yang Liu ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02334 ,  H01L21/0206 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

Abstract translation: 氧化物的清洗方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域的基板上形成第一氧化物层。 在第一区域和第二区域的第一氧化物层上进行含有氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2）的工艺。 光致抗蚀剂层覆盖第一区域的第一氧化物层，同时暴露第二区域的第一氧化物层。 去除第二区域的第一氧化物层。 然后除去光致抗蚀剂层。

公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.