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    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM
    15.
    发明申请
    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM 有权
    正确的配置数据压缩和解密系统

    公开(公告)号：US20150058695A1

    公开(公告)日：2015-02-26

    申请号：US13972812

    申请日：2013-08-21

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Dinesh K. Jain

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G06F11/10 ,  H03M7/702 ,  H03M13/05

    Abstract: An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

    Abstract translation: 一种装置具有共享熔丝阵列和多个微处理器核心。 共享保险丝阵列设置在管芯上，共享保险丝阵列具有多个半导体保险丝，其编程有压缩配置数据和错误校验（ECC）代码。 多个微处理器核心设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化 多个核心中的每一个。 所述多个核心中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的错误，以解压缩所有经校正的压缩配置数据，并且分发解压缩配置 数据初始化元素。

    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION
    16.
    发明申请
    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 审中-公开
    扩展高速缓存校正的设备和方法

    公开(公告)号：US20150058564A1

    公开(公告)日：2015-02-26

    申请号：US13972481

    申请日：2013-08-21

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Dinesh K. Jain

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/0802 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1008 ,  G06F15/76 ,  G11C29/787 ,  G11C29/802

    Abstract: An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

    Abstract translation: 一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。 半导体熔丝阵列设置在芯片上，其中编程了配置数据。 半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。 高速缓冲存储器设置在管芯上。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存 校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM
    18.
    发明申请
    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM 有权
    不对称多核心处理器与本地切换机制

    公开(公告)号：US20140298060A1

    公开(公告)日：2014-10-02

    申请号：US14077740

    申请日：2013-11-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

    IPC: G06F1/32

    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

    Abstract translation: 处理器包括被配置为支持其指令集体系结构（ISA）特征集的特征的第一和第二相应子集的第一和第二处理核心。 第一个子集小于ISA功能集的所有功能。 第一个和第二个子集是不同的，但它们的联合是ISA功能集的所有功能。 第一核心在由第一核心而不是第二核心执行的同时检测线程，尝试使用不在第一子集中的特征，并且响应地指示从第一核到第二核的切换以执行 线程。 不支持的功能可能是不支持的指令或操作模式。 如果较低性能/功率核心被过度利用或较高性能/功率核心利用不足，也可能产生开关。

    REVOKEABLE MSR PASSWORD PROTECTION
    19.
    发明申请
    REVOKEABLE MSR PASSWORD PROTECTION 有权
    可靠的MSR密码保护

    公开(公告)号：US20140059358A1

    公开(公告)日：2014-02-27

    申请号：US14053953

    申请日：2013-10-15

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F12/14

    CPC classification number: G06F12/1408 ,  G06F9/30076 ,  G06F9/30101 ,  G06F21/31 ,  G06F21/71 ,  G06F21/78 ,  G06F21/79

    Abstract: A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.

    Abstract translation: 微处理器包括具有地址的型号特定寄存器（MSR），具有第一预定值制造的保险丝和控制寄存器。 微处理器首先将第一预定值从保险丝加载到控制寄存器中。 在最初将第一预定值加载到控制寄存器之后，微处理器还从包括微处理器的计算机系统的系统软件接收第二预定值。 微处理器通过提供通过利用在微处理器的第一实例中制造的秘密密钥加密第一预定值和MSR地址的功能产生的第一密码的指令来禁止对MSR的访问，并使得能够通过指令访问MSR 其提供通过用秘密密钥加密第二预定值的功能和MSR地址产生的第二密码。

    Microprocessor that fuses if-then instructions
    20.
    发明授权
    Microprocessor that fuses if-then instructions 有权

    公开(公告)号：US10394562B2

    公开(公告)日：2019-08-27

    申请号：US15728551

    申请日：2017-10-10

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A microprocessor performs an If-Then (IT) instruction and an associated IT block by extracting condition information from the IT instruction and for each instruction of the IT block: determining a respective condition for the instruction using the extract condition information, translating the instruction into a microinstruction, and conditionally executing the microinstruction based on the respective condition. For a first instruction, the translating comprises fusing the IT instruction with the first IT block instruction. A hardware instruction translation unit performs the extracting, determining and translating. Execution units conditionally execute the microinstructions. The hardware instruction translation unit and execution units are distinct hardware elements and are coupled together. The hardware translation unit performs the extracting, fusing and for each instruction of the IT block the determining and translating without writing intermediate results to a system memory, without execution of other architectural instructions by the microprocessor, and/or in six clock cycles or less.

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