公开(公告)号：US08435892B2

公开(公告)日：2013-05-07

申请号：US12908521

申请日：2010-10-20

申请人： Atsuo Isobe ,  Keiko Saito ,  Tomohiko Sato

发明人： Atsuo Isobe ,  Keiko Saito ,  Tomohiko Sato

IPC分类号： H01L21/44

CPC分类号： H01L29/4908 ,  H01L29/66757 ,  H01L29/78621

摘要： It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×1020/cm3 or less) that is included in a deeper region than predetermined depth, and a second range of a concentration of the impurity element (more than 1×1020/cm3) that is included in a shallower region than the predetermined depth; and a deeper region than a portion in contact with the electrode or the wiring in the semiconductor film is in the first range of the concentration of the impurity element.

摘要翻译： 本说明书中公开的发明的目的是提供具有低接触电阻的晶体管。 在晶体管中，包括赋予P型或N型导电性的杂质元素的半导体膜，形成在其上的绝缘膜，以及电极或布线，其通过至少形成在所述半导体膜上的接触孔与半导体膜电连接 包括绝缘膜; 半导体膜具有包含在比预定深度更深的区域中的杂质元素的浓度的第一范围（1×10 20 / cm 3以下），并且杂质元素的浓度的第二范围（大于1× 1020 / cm3），其被包括在比预定深度更浅的区域中; 并且比半导体膜中与电极或布线接触的部分更深的区域在杂质元素的浓度的第一范围内。

公开(公告)号：US20120302377A1

公开(公告)日：2012-11-29

申请号：US13376982

申请日：2010-06-09

申请人： Tomohiko Sato ,  Sunao Umemura ,  Yutaka Kawata ,  Mitsuhiro Saso

发明人： Tomohiko Sato ,  Sunao Umemura ,  Yutaka Kawata ,  Mitsuhiro Saso

IPC分类号： A63B37/14

CPC分类号： A63B37/0004 ,  A63B37/0007 ,  A63B37/0008 ,  A63B37/0012 ,  A63B37/0019 ,  A63B37/002

摘要： A golf ball provided with elliptical dimples. A golf ball provided with non-circular dimples, configured by forming the dimples in the surface of a sphere or of a pseudosphere which consists of a polyhedron. The dimples have a non-circular shape which has a major axis having a length at least 1.2 times greater than that of the minor axis of the shape, are each composed of a pair of circular arcs, and have a depth which causes the peripheral edges of the dimples to generate turbulence. The configuration reduces the separation width at the separation boundary to a level less than that of a golf ball having circular dimples, and this decreases the drag. The polyhedron can be substantially composed of triangles, pentagons, or hexagons.

摘要翻译： 高尔夫球提供椭圆形凹坑。 设置有非圆形凹坑的高尔夫球，通过在球体或由多面体构成的假球的表面中形成凹坑来构造。 凹坑具有非圆形形状，其长轴的长度比形状的短轴的长度大至少1.2倍，均由一对圆弧组成，并且具有使周边边缘 的凹坑产生湍流。 该配置将分离边界处的分离宽度减小到具有圆形凹坑的高尔夫球的分离宽度，这降低了阻力。 多面体可以基本上由三角形，五边形或六边形组成。

公开(公告)号：USD662623S1

公开(公告)日：2012-06-26

申请号：US29398773

申请日：2011-08-04

申请人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

设计人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

公开(公告)号：US20060284184A1

公开(公告)日：2006-12-21

申请号：US11513300

申请日：2006-08-31

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  G02F1/13454 ,  G09G3/3648 ,  G09G3/3688 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

摘要： The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside the pseudo single crystal regions. Two or more of the plurality of thin film transistors, which are required to exhibit small irregularities relative to each other as characteristics thereof, have the direction of the length of the gates of the respective thin film transistors arranged at an inclination of within ±20 degree with respect to the longitudinal direction of the strip-like grown crystals, and they are arranged such that, when channel regions of respective thin film transistors are imaginarily extended in parallel to the growth direction of the strip-like grown crystals, at least portions of the channel regions are superposed on each other.

摘要翻译： 通过伪单结晶技术制备的一对晶体管的特性不均匀性降低。 为了实现这一点，半导体层形成在基板上并且在其中具有伪单晶区域，并且多个薄膜晶体管布置在伪单晶区域内部。 多个薄膜晶体管中的两个或更多个需要以相对于彼此的特性表现出小的不规则性，其各自的薄膜晶体管的栅极的长度方向以±20度的倾斜度 相对于带状生长晶体的纵向方向，并且它们被布置成使得当相应的薄膜晶体管的沟道区域被想象地平行于条状生长晶体的生长方向延伸时，至少部分 通道区域彼此重叠。

公开(公告)号：US07102170B2

公开(公告)日：2006-09-05

申请号：US10743706

申请日：2003-12-24

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  G02F1/13454 ,  G09G3/3648 ,  G09G3/3688 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

摘要： The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside of the pseudo single crystal regions. Two or more of the plurality of thin film transistors, which are required to exhibit small irregularities relative to each other as characteristics thereof, have the direction of the length of the gates of the respective thin film transistors arranged at an inclination of within ±20 degree with respect to the longitudinal direction of the strip-like grown crystals, and they are arranged such that, when channel regions of respective thin film transistors are imaginarily extended in parallel to the growth direction of the strip-like grown crystals, at least portions of the channel regions are superposed on each other.

摘要翻译： 通过伪单结晶技术制备的一对晶体管的特性不均匀性降低。 为了实现这一点，半导体层形成在基板上并且在其中具有伪单晶区域，并且多个薄膜晶体管布置在伪单晶区域的内部。 多个薄膜晶体管中的两个或更多个需要以相对于彼此的特性表现出小的不规则性，其各自的薄膜晶体管的栅极的长度方向以±20度的倾斜度 相对于带状生长晶体的纵向方向，并且它们被布置成使得当相应的薄膜晶体管的沟道区域被想象地平行于条状生长晶体的生长方向延伸时，至少部分 通道区域彼此重叠。

公开(公告)号：US20050248010A1

公开(公告)日：2005-11-10

申请号：US11080545

申请日：2005-03-16

申请人： Takao Ono ,  Tomohiko Sato ,  Hironori Iwasaki

发明人： Takao Ono ,  Tomohiko Sato ,  Hironori Iwasaki

IPC分类号： H01L23/12 ,  H01L23/02 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/02 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09172 ,  H05K2201/10159 ,  H05K2201/10515 ,  Y02P70/613 ,  H01L2924/00

摘要： A thermal expansion coefficient of a module substrate 8 is different from that of a package substrate. There is not any place where stresses generated in Interfaces between soldering balls 5 and the substrate are released. These stresses are largely applied to soldering bond, the soldering balls are strained, deformed, or cracked, and there has been a problem in long-time reliability. Slits are disposed on opposite sides of each soldering ball in a vertical direction to a side in an outer peripheral side of the package substrate, accordingly the stresses applied to the soldering balls are weakened, and the soldering balls are prevented from being strained, deformed, or cracked. When soldering strains are reduced in this manner, there can be provided a surface mounting type semiconductor package and system module having high reliability, low cost, and satisfactory electric characteristics such as low capacitance and low inductance.

摘要翻译： 模块基板8的热膨胀系数与封装基板的热膨胀系数不同。 没有任何地方在焊球5和基板之间的接口中产生应力释放。 这些应力主要用于焊接，焊球变形，变形或破裂，长时间的可靠性存在问题。 在每个焊球的相对侧，在与封装基板的外周侧的一侧的垂直方向上配置有狭缝，因此施加于焊球的应力变弱，防止焊球发生变形， 或破裂。 当以这种方式减小焊接应变时，可以提供具有高可靠性，低成本和令人满意的电特性如低电容和低电感的表面安装型半导体封装和系统模块。

公开(公告)号：US20050230829A1

公开(公告)日：2005-10-20

申请号：US11081658

申请日：2005-03-17

申请人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

发明人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

IPC分类号： H05K1/02 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K1/111 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09281 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.

摘要翻译： 半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。 在封装基板5上形成有多个列，其中布置有多个焊盘8。 构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。 互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线 封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

公开(公告)号：US20050116654A1

公开(公告)日：2005-06-02

申请号：US10998002

申请日：2004-11-29

申请人： Hideo Sato ,  Tomohiko Sato ,  Masahiro Maki ,  Takayuki Nakao

发明人： Hideo Sato ,  Tomohiko Sato ,  Masahiro Maki ,  Takayuki Nakao

IPC分类号： G02F1/133 ,  G09G3/10 ,  G09G3/20 ,  G09G3/36 ,  H04N5/66

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0259 ,  G09G2310/027

摘要： Gamma correction of a video signal voltage applied to respective pixels of a display device can be accomplished without modulating a ramp voltage. The display device includes a common voltage generating circuit which selectively outputs a high-potential-side common voltage or a low-potential-side common voltage to common electrodes in response to an alternating signal, a data storage circuit, a reference data generating circuit which a ramp voltage generating circuit, a plurality of comparing circuits which compare data stored in the data storage circuit and the reference data generated by the reference data generating circuit, and a plurality of sampling circuits which sample the ramp voltage generated by the ramp voltage generating circuit in response to comparison results of the comparing circuits and output the sampled ramp voltage as a video signal voltage to respective video lines. The reference data generated by the reference data generating circuit is changed non-linearly with respect to time.

摘要翻译： 可以在不调制斜坡电压的情况下实现施加到显示装置的各个像素的视频信号电压的伽马校正。 显示装置包括：公共电压发生电路，其响应于交变信号选择性地向公共电极输出高电位侧公共电压或低电位侧公共电压;数据存储电路，参考数据生成电路， 斜坡电压产生电路，将数据存储电路中存储的数据与由基准数据产生电路产生的参考数据进行比较的多个比较电路，以及对由斜坡电压产生电路产生的斜坡电压进行采样的多个采样电路 响应于比较电路的比较结果，并将采样的斜坡电压作为视频信号电压输出到各个视频线。 由参考数据产生电路产生的参考数据相对于时间非线性地改变。

公开(公告)号：US06756661B2

公开(公告)日：2004-06-29

申请号：US09800503

申请日：2001-03-08

申请人： Kensuke Tsuneda ,  Toshio Sugano ,  Seiichiro Tsukui ,  Kouji Nagaoka ,  Tomohiko Sato

发明人： Kensuke Tsuneda ,  Toshio Sugano ,  Seiichiro Tsukui ,  Kouji Nagaoka ,  Tomohiko Sato

IPC分类号： H01L23495

CPC分类号： H01L23/49811 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/50

摘要： A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

摘要翻译： 装载有四个芯片（1组16位型）的存储器TCP由一层双层布线层结构的磁带，安装在该磁带上的四个芯片等构成。公共信号端子布置在一组两个相对的 侧，另一侧设置独立的信号端子。 两侧的公共信号端子彼此电连接公共信号线。 此外，在将该存储器TCP安装到基板的前侧和后侧的DIMM中，在矩形基板的一个长边上形成有多个外部端子，并且安装存储器TCP，使得存储器的独立信号端子 沿着这些外部端子的排列方向布置TCP。

公开(公告)号：US06635589B2

公开(公告)日：2003-10-21

申请号：US09286999

申请日：1999-04-07

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Mitsunori Sakama ,  Tomohiko Sato ,  Satoshi Teramoto ,  Shigefumi Sakai

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Mitsunori Sakama ,  Tomohiko Sato ,  Satoshi Teramoto ,  Shigefumi Sakai

IPC分类号： H01L2142

CPC分类号： H01L21/28158 ,  C23C14/58 ,  C23C16/56 ,  H01L29/66757 ,  Y10S438/909 ,  Y10S438/91 ,  Y10S438/958

摘要： Silicon oxide films which are good as gate insulation films are formed by subjecting a silicon oxide film which has been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in a dinitrogen monoxide atmosphere, or in an NH3 or N2H4 atmosphere, while irradiating with ultraviolet light, reducing the hydrogen and carbon contents in the silicon oxide film and introducing nitrogen into the boundary with the silicon film in particular. Furthermore, silicon oxide films which are good as gate insulating films have been formed by subjecting silicon oxide films which have been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in an N2O atmosphere (or hydrogen nitride atmosphere) while irradiating with ultraviolet light, and then carrying out a heat treatment at 300-700° C. in a hydrogen nitride atmosphere (N2O atmosphere), and reducing the amount of hydrogen and carbon in the silicon oxide film and introducing nitrogen into the boundary with the silicon film in particular.

摘要翻译： 作为栅极绝缘膜良好的氧化硅膜通过在300-700℃下通过PVD法或CVD法对形成在包含硅膜的有源层上的氧化硅膜进行热处理而形成。 在一氧化二氮气氛中，或在NH 3或N 2 H 4气氛中，同时用紫外线照射，降低氧化硅膜中的氢和碳含量，并将氮引入与硅膜的边界。 此外，作为栅极绝缘膜良好的氧化硅膜已经通过利用PVD法或CVD法在由硅膜的活性层上形成的氧化硅膜在300-700°的温度下进行热处理而形成 在氮氧化物气氛（N 2 O气氛）中在N2O气氛（或氮化氢气氛）中照射紫外线，然后在300-700℃下进行热处理，并减少氢和碳的量 在氧化硅膜中，特别是将氮引入与硅膜的边界。