公开(公告)号：US20050248010A1

公开(公告)日：2005-11-10

申请号：US11080545

申请日：2005-03-16

申请人： Takao Ono ,  Tomohiko Sato ,  Hironori Iwasaki

发明人： Takao Ono ,  Tomohiko Sato ,  Hironori Iwasaki

IPC分类号： H01L23/12 ,  H01L23/02 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/02 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09172 ,  H05K2201/10159 ,  H05K2201/10515 ,  Y02P70/613 ,  H01L2924/00

摘要： A thermal expansion coefficient of a module substrate 8 is different from that of a package substrate. There is not any place where stresses generated in Interfaces between soldering balls 5 and the substrate are released. These stresses are largely applied to soldering bond, the soldering balls are strained, deformed, or cracked, and there has been a problem in long-time reliability. Slits are disposed on opposite sides of each soldering ball in a vertical direction to a side in an outer peripheral side of the package substrate, accordingly the stresses applied to the soldering balls are weakened, and the soldering balls are prevented from being strained, deformed, or cracked. When soldering strains are reduced in this manner, there can be provided a surface mounting type semiconductor package and system module having high reliability, low cost, and satisfactory electric characteristics such as low capacitance and low inductance.

摘要翻译： 模块基板8的热膨胀系数与封装基板的热膨胀系数不同。 没有任何地方在焊球5和基板之间的接口中产生应力释放。 这些应力主要用于焊接，焊球变形，变形或破裂，长时间的可靠性存在问题。 在每个焊球的相对侧，在与封装基板的外周侧的一侧的垂直方向上配置有狭缝，因此施加于焊球的应力变弱，防止焊球发生变形， 或破裂。 当以这种方式减小焊接应变时，可以提供具有高可靠性，低成本和令人满意的电特性如低电容和低电感的表面安装型半导体封装和系统模块。

公开(公告)号：US07633147B2

公开(公告)日：2009-12-15

申请号：US10672551

申请日：2003-09-26

申请人： Seiji Funaba ,  Hisashi Abo ,  Takao Ono ,  Koji Hosokawa ,  Yoji Nishio ,  Atsushi Nakamura ,  Tomohiko Sato

发明人： Seiji Funaba ,  Hisashi Abo ,  Takao Ono ,  Koji Hosokawa ,  Yoji Nishio ,  Atsushi Nakamura ,  Tomohiko Sato

IPC分类号： H01L23/538

CPC分类号： H01L25/105 ,  H01L23/50 ,  H01L23/552 ,  H01L23/60 ,  H01L23/64 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H05K1/112 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

摘要翻译： 构成存储器件的半导体单元具有存储芯片，具有三个布线层的封装基板。 电源表面（VDD表面）和（GND表面）被布线在封装衬底上，而封装内的DQ总线布线在两个电源表面之间的中间层上。 存储器件每一个封装内DQ总线具有两个DQ引脚。 封装内的DQ总线通过通孔连接到存储器芯片的信号端子焊盘。 鉴于两个DW引脚，用于将封装内DQ DQ总线与信号端子焊盘连接的通孔构成分支线。

公开(公告)号：USD685505S1

公开(公告)日：2013-07-02

申请号：US29397934

申请日：2011-07-22

申请人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

设计人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

公开(公告)号：US08435892B2

公开(公告)日：2013-05-07

申请号：US12908521

申请日：2010-10-20

申请人： Atsuo Isobe ,  Keiko Saito ,  Tomohiko Sato

发明人： Atsuo Isobe ,  Keiko Saito ,  Tomohiko Sato

IPC分类号： H01L21/44

CPC分类号： H01L29/4908 ,  H01L29/66757 ,  H01L29/78621

摘要： It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×1020/cm3 or less) that is included in a deeper region than predetermined depth, and a second range of a concentration of the impurity element (more than 1×1020/cm3) that is included in a shallower region than the predetermined depth; and a deeper region than a portion in contact with the electrode or the wiring in the semiconductor film is in the first range of the concentration of the impurity element.

摘要翻译： 本说明书中公开的发明的目的是提供具有低接触电阻的晶体管。 在晶体管中，包括赋予P型或N型导电性的杂质元素的半导体膜，形成在其上的绝缘膜，以及电极或布线，其通过至少形成在所述半导体膜上的接触孔与半导体膜电连接 包括绝缘膜; 半导体膜具有包含在比预定深度更深的区域中的杂质元素的浓度的第一范围（1×10 20 / cm 3以下），并且杂质元素的浓度的第二范围（大于1× 1020 / cm3），其被包括在比预定深度更浅的区域中; 并且比半导体膜中与电极或布线接触的部分更深的区域在杂质元素的浓度的第一范围内。

公开(公告)号：US20120302377A1

公开(公告)日：2012-11-29

申请号：US13376982

申请日：2010-06-09

申请人： Tomohiko Sato ,  Sunao Umemura ,  Yutaka Kawata ,  Mitsuhiro Saso

发明人： Tomohiko Sato ,  Sunao Umemura ,  Yutaka Kawata ,  Mitsuhiro Saso

IPC分类号： A63B37/14

CPC分类号： A63B37/0004 ,  A63B37/0007 ,  A63B37/0008 ,  A63B37/0012 ,  A63B37/0019 ,  A63B37/002

摘要： A golf ball provided with elliptical dimples. A golf ball provided with non-circular dimples, configured by forming the dimples in the surface of a sphere or of a pseudosphere which consists of a polyhedron. The dimples have a non-circular shape which has a major axis having a length at least 1.2 times greater than that of the minor axis of the shape, are each composed of a pair of circular arcs, and have a depth which causes the peripheral edges of the dimples to generate turbulence. The configuration reduces the separation width at the separation boundary to a level less than that of a golf ball having circular dimples, and this decreases the drag. The polyhedron can be substantially composed of triangles, pentagons, or hexagons.

摘要翻译： 高尔夫球提供椭圆形凹坑。 设置有非圆形凹坑的高尔夫球，通过在球体或由多面体构成的假球的表面中形成凹坑来构造。 凹坑具有非圆形形状，其长轴的长度比形状的短轴的长度大至少1.2倍，均由一对圆弧组成，并且具有使周边边缘 的凹坑产生湍流。 该配置将分离边界处的分离宽度减小到具有圆形凹坑的高尔夫球的分离宽度，这降低了阻力。 多面体可以基本上由三角形，五边形或六边形组成。

公开(公告)号：USD662623S1

公开(公告)日：2012-06-26

申请号：US29398773

申请日：2011-08-04

申请人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

设计人： Junichiro Yamamoto ,  Shigeru Osawa ,  Yuichiro Takahara ,  Tomohiko Sato

公开(公告)号：US20110007060A1

公开(公告)日：2011-01-13

申请号：US12828432

申请日：2010-07-01

申请人： Werapong Jarupoonphol ,  Takeya Takeuchi ,  Tomohiko Sato

发明人： Werapong Jarupoonphol ,  Takeya Takeuchi ,  Tomohiko Sato

IPC分类号： G09G5/00

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2310/08 ,  G09G2320/0247

摘要： A liquid crystal display device is provided, which may reduce flicker in all display gray levels. The liquid crystal display device includes a scan line drive circuit, a signal line drive circuit and a common connection line drive circuit. The common connection line drive circuit applies a voltage, the voltage having polarity opposite to polarity of the signal line, to a common connection line corresponding to a liquid crystal element as a selection object in a write period for writing into the liquid crystal element as a selection object, and applies one or multiple voltages, each voltage having a value different from a center value between an upper limit value and a lower limit value of voltages applied to the common connection lines in the write period, to the common connection lines in a holding period after writing into the liquid crystal element as a selection object is performed.

摘要翻译： 提供了一种可以减少所有显示灰度级闪烁的液晶显示装置。 液晶显示装置包括扫描线驱动电路，信号线驱动电路和公共连接线驱动电路。 公共连接线路驱动电路将与极性相反的电压作为选择对象施加到与液晶元件对应的公共连接线上，该写入期间写入液晶元件为 选择对象，并且施加一个或多个电压，每个电压具有不同于在写入周期中施加到公共连接线的电压的上限值和下限值之间的中心值的值到一个或多个电压中的公共连接线 写入作为选择对象的液晶元件之后的保持期间被执行。

公开(公告)号：US20100271359A1

公开(公告)日：2010-10-28

申请号：US12760284

申请日：2010-04-14

申请人： Takeya Takeuchi ,  Werapong Jarupoonphol ,  Tomohiko Sato ,  Yoshitoshi Kida

发明人： Takeya Takeuchi ,  Werapong Jarupoonphol ,  Tomohiko Sato ,  Yoshitoshi Kida

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2330/021

摘要： The present invention provides a liquid crystal display device including: a pixel array including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, a plurality of liquid crystal elements arranged in a matrix corresponding to an intersection of each scanning line and each signal line, and a plurality of common connection lines arranged one by one corresponding to the liquid crystal elements of each line; a scanning line drive circuit; a signal line drive circuit; and a common connection line drive circuit electrically separating, from each other, one or a plurality of common connection lines (first common connection lines), and a plurality of common connection lines (second common connection lines), and electrically connecting the plurality of second common connection lines to each other to independently drive the first common connection line and the second connection lines from each other.

摘要翻译： 本发明提供一种液晶显示装置，包括：像素阵列，包括排列成行的多条扫描线，多列排列的信号线，多个液晶元件排列成与每个扫描的交点相对应的矩阵 线和每个信号线，以及与每行的液晶元件对应地排列的多个公共连接线; 扫描线驱动电路; 信号线驱动电路; 以及公共连接线驱动电路，其将一个或多个公共连接线（第一公共连接线）和多个公共连接线（第二公共连接线）彼此电分离，并且电连接所述多个第二 公共连接线彼此独立地驱动第一公共连接线和第二连接线彼此。

公开(公告)号：US20060284184A1

公开(公告)日：2006-12-21

申请号：US11513300

申请日：2006-08-31

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  G02F1/13454 ,  G09G3/3648 ,  G09G3/3688 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

摘要： The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside the pseudo single crystal regions. Two or more of the plurality of thin film transistors, which are required to exhibit small irregularities relative to each other as characteristics thereof, have the direction of the length of the gates of the respective thin film transistors arranged at an inclination of within ±20 degree with respect to the longitudinal direction of the strip-like grown crystals, and they are arranged such that, when channel regions of respective thin film transistors are imaginarily extended in parallel to the growth direction of the strip-like grown crystals, at least portions of the channel regions are superposed on each other.

摘要翻译： 通过伪单结晶技术制备的一对晶体管的特性不均匀性降低。 为了实现这一点，半导体层形成在基板上并且在其中具有伪单晶区域，并且多个薄膜晶体管布置在伪单晶区域内部。 多个薄膜晶体管中的两个或更多个需要以相对于彼此的特性表现出小的不规则性，其各自的薄膜晶体管的栅极的长度方向以±20度的倾斜度 相对于带状生长晶体的纵向方向，并且它们被布置成使得当相应的薄膜晶体管的沟道区域被想象地平行于条状生长晶体的生长方向延伸时，至少部分 通道区域彼此重叠。

公开(公告)号：US07102170B2

公开(公告)日：2006-09-05

申请号：US10743706

申请日：2003-12-24

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Tomohiko Sato ,  Mutsuko Hatano

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  G02F1/13454 ,  G09G3/3648 ,  G09G3/3688 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

摘要： The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside of the pseudo single crystal regions. Two or more of the plurality of thin film transistors, which are required to exhibit small irregularities relative to each other as characteristics thereof, have the direction of the length of the gates of the respective thin film transistors arranged at an inclination of within ±20 degree with respect to the longitudinal direction of the strip-like grown crystals, and they are arranged such that, when channel regions of respective thin film transistors are imaginarily extended in parallel to the growth direction of the strip-like grown crystals, at least portions of the channel regions are superposed on each other.

摘要翻译： 通过伪单结晶技术制备的一对晶体管的特性不均匀性降低。 为了实现这一点，半导体层形成在基板上并且在其中具有伪单晶区域，并且多个薄膜晶体管布置在伪单晶区域的内部。 多个薄膜晶体管中的两个或更多个需要以相对于彼此的特性表现出小的不规则性，其各自的薄膜晶体管的栅极的长度方向以±20度的倾斜度 相对于带状生长晶体的纵向方向，并且它们被布置成使得当相应的薄膜晶体管的沟道区域被想象地平行于条状生长晶体的生长方向延伸时，至少部分 通道区域彼此重叠。