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    IC die with dummy structures
    11.
    发明授权
    IC die with dummy structures 有权

    公开(公告)号：US11114344B1

    公开(公告)日：2021-09-07

    申请号：US16805398

    申请日：2020-02-28

    Applicant: XILINX, INC.

    Inventor： Hui-Wen Lin ,  Nui Chong ,  Myongseob Kim ,  Henley Liu ,  Ping-Chin Yeh ,  Cheang-whang Chang

    IPC: H01L21/82 ,  H01L23/50 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

    Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

    Methods of interconnect for high density 2.5D and 3D integration
    13.
    发明授权
    Methods of interconnect for high density 2.5D and 3D integration 有权

    公开(公告)号：US10593638B2

    公开(公告)日：2020-03-17

    申请号：US15473294

    申请日：2017-03-29

    Applicant: Xilinx, Inc.

    Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

    Integrated circuit device with stacked dies having mirrored circuitry
    18.
    发明授权
    Integrated circuit device with stacked dies having mirrored circuitry 有权

    公开(公告)号：US11205639B2

    公开(公告)日：2021-12-21

    申请号：US16798267

    申请日：2020-02-21

    Applicant: XILINX, INC.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

    IPC: H01L21/50 ,  H01L25/065 ,  H01L25/00

    Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

    Test circuits for testing a die stack
    19.
    发明授权
    Test circuits for testing a die stack 有权

    公开(公告)号：US11054461B1

    公开(公告)日：2021-07-06

    申请号：US16351310

    申请日：2019-03-12

    Applicant: Xilinx, Inc.

    Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

    Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

    PACKAGE INTEGRATION FOR MEMORY DEVICES
    20.
    发明申请
    PACKAGE INTEGRATION FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200303341A1

    公开(公告)日：2020-09-24

    申请号：US16361617

    申请日：2019-03-22

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

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