公开(公告)号：US20230230933A1

公开(公告)日：2023-07-20

申请号：US18149029

申请日：2022-12-30

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Chaung-Lin LAI ,  Shu-Ming CHANG ,  Tsang-Yu LIU

IPC: H01L23/544 ,  H01L27/146

CPC classification number: H01L23/544 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2223/54433

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

公开(公告)号：US20150097299A1

公开(公告)日：2015-04-09

申请号：US14504319

申请日：2014-10-01

Applicant: XINTEC INC.

Inventor： Chien-Hui CHEN ,  Tsang-Yu LIU ,  Chun-Wei CHANG ,  Chia-Ming CHENG

IPC: H01L25/065 ,  H01L21/50

CPC classification number: H01L25/0655 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

Abstract translation: 提供一种形成芯片封装的方法。 提供第一基板。 第二衬底附接在第一衬底上，其中第二衬底具有由划线区域分隔的多个矩形芯片区域。 去除对应于划线区域的第二基板的一部分，以在第一基板上形成多个芯片，其中在相邻芯片之间形成至少一个桥接部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US20140327152A1

公开(公告)日：2014-11-06

申请号：US14337011

申请日：2014-07-21

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract translation: 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。

公开(公告)号：US20140312482A1

公开(公告)日：2014-10-23

申请号：US14255872

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chun-Wei CHANG ,  Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN ,  Chien-Hui CHEN ,  Tsang-Yu LIU

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract translation: 提供晶片级的芯片阵列。 晶片级的芯片阵列包括半导体晶片和至少一个延伸线保护。 半导体晶片具有彼此相邻布置的至少两个芯片和载体层。 每个芯片具有上表面和下表面，并且包括至少一个装置。 该装置设置在上表面上，被载体层覆盖。 延伸线保护设置在载体层之下和两个芯片之间。 延长线保护的厚度小于芯片的厚度。 其中延伸线保护件中至少有一条延伸线。 此外，还提供了由晶片级阵列芯片制造的芯片封装及其方法。

公开(公告)号：US20130196470A1

公开(公告)日：2013-08-01

申请号：US13802262

申请日：2013-03-13

Applicant: XINTEC INC.

Inventor： Chia-Lun TSAI ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/76898 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/023 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

Abstract translation: 芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中 所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

公开(公告)号：US20130119556A1

公开(公告)日：2013-05-16

申请号：US13678507

申请日：2012-11-15

Applicant: Xintec Inc.

Inventor： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract translation: 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫，并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。

公开(公告)号：US20230369528A1

公开(公告)日：2023-11-16

申请号：US18307004

申请日：2023-04-26

Applicant: Xintec Inc.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L31/12 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/0216 ,  H01L31/02 ,  H01L31/16

CPC classification number: H01L31/125 ,  H01L31/1876 ,  H01L31/02327 ,  H01L31/0216 ,  H01L31/02002 ,  H01L31/16

Abstract: A chip package includes a chip, a first support layer, a light emitter, a first light transmissive sheet, a redistribution layer, and a conductive structure. A top surface of the chip has a conductive pad and a first light receiver. The first support layer is located on the top surface of the chip. The light emitter is located on the top surface of the chip. The first light transmissive sheet is located on the first support layer and covers the first light receiver. The redistribution layer is electrically connected to the conductive pad and extends to a bottom surface of the chip. The conductive structure is located on the redistribution layer that is on the bottom surface of the chip.

公开(公告)号：US20230369362A1

公开(公告)日：2023-11-16

申请号：US18312552

申请日：2023-05-04

Applicant: Xintec Inc.

Inventor： Po-Han LEE ,  Tsang Yu LIU ,  Chia-Ming CHENG ,  Kuei Wei CHEN ,  Jiun-Yen LAI

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L27/14687 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/29011 ,  H01L2224/94 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/33181 ,  H01L2224/33051 ,  H01L24/33

Abstract: A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.

公开(公告)号：US20230238408A1

公开(公告)日：2023-07-27

申请号：US18077152

申请日：2022-12-07

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/16225 ,  H01L24/16

Abstract: A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.

公开(公告)号：US20200098811A1

公开(公告)日：2020-03-26

申请号：US16581594

申请日：2019-09-24

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.