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41 条记录 (耗时 0.031 秒)

    Chip package and method for fabricating the same
    12.
    发明授权
    Chip package and method for fabricating the same 有权
    芯片封装及其制造方法

    公开(公告)号：US08575634B2

    公开(公告)日：2013-11-05

    申请号：US12981600

    申请日：2010-12-30

    申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    IPC分类号： H01L33/60 ,  H01L33/48

    CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

    摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

    LIGHT EMITTING DIODE PACKAGE AND METHOD FOR FORMING THE SAME
    14.
    发明申请
    LIGHT EMITTING DIODE PACKAGE AND METHOD FOR FORMING THE SAME 有权
    发光二极管封装及其形成方法

    公开(公告)号：US20110169042A1

    公开(公告)日：2011-07-14

    申请号：US12687497

    申请日：2010-01-14

    申请人： Shang-Yi WU ,  Tsang-Yu Liu

    发明人： Shang-Yi WU ,  Tsang-Yu Liu

    IPC分类号： H01L33/00 ,  H01L21/50

    CPC分类号： H01L33/642 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L24/48 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A light emitting diode package is provided, which includes a semiconductor substrate having a first surface and a second surface; at least a through-hole passing through the semiconductor substrate; a thermal via formed extending from the second surface toward the first surface of the semiconductor substrate, wherein the thermal via has a first end near the first surface and a second end near the second surface; an insulating layer overlying a sidewall of the through-hole and extending overlying the first surface and the second surface of the semiconductor substrate, wherein the insulating layer further covers at least one of the first end, the second end and a sidewall of the thermal via; a conducting layer overlying the insulating layer in the through-hole and extending to the first surface and the second surface of the semiconductor substrate; and an LED chip disposed overlying the semiconductor substrate.

    摘要翻译： 提供一种发光二极管封装，其包括具有第一表面和第二表面的半导体衬底; 至少穿过所述半导体衬底的通孔; 所述热通孔从所述第二表面延伸到所述半导体衬底的所述第一表面，其中所述热通孔具有靠近所述第一表面的第一端和靠近所述第二表面的第二端; 绝缘层，其覆盖所述通孔的侧壁并延伸覆盖所述半导体衬底的所述第一表面和所述第二表面，其中所述绝缘层还覆盖所述热通孔的所述第一端，所述第二端和侧壁中的至少一个 ; 覆盖所述通孔中的所述绝缘层并延伸到所述半导体衬底的所述第一表面和所述第二表面的导电层; 以及设置在半导体衬底上的LED芯片。

    Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation
    15.
    发明授权
    Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation 有权
    用于应变松弛的缓冲区的热应变诱导的铜小丘的解决方案

    公开(公告)号：US06897147B1

    公开(公告)日：2005-05-24

    申请号：US10758315

    申请日：2004-01-15

    申请人： Shin-Yeu Tsai ,  Po-Hsiung Leu ,  Chia-Ming Yang ,  Tsang-Yu Liu ,  Yun-Da Fan ,  Chen-Peng Fan

    发明人： Shin-Yeu Tsai ,  Po-Hsiung Leu ,  Chia-Ming Yang ,  Tsang-Yu Liu ,  Yun-Da Fan ,  Chen-Peng Fan

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76838

    摘要： A method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by applying F ions to the copper layer to form a buffer zone on a surface of the copper layer and in-situ depositing a capping layer overlying the copper layer. The F ions remove copper oxide naturally formed on the copper surface and the buffer zone transfers thermal vertical strain in the copper to horizontal strain thereby preventing formation of copper hillocks.

    摘要翻译： 描述了一种在铜金属化中减少铜小丘的方法。 通过覆盖晶片上的衬底的电介质层形成开口。 形成覆盖在电介质层上并完全填充开口的铜层。 铜层被抛光回去，仅在开口内留下铜层。 通过将铜离子施加到铜层以在铜层的表面上形成缓冲区并原位沉积覆盖铜层的覆盖层来减少铜小丘。 F离子去除在铜表面上自然形成的氧化铜，缓冲区将铜中的热垂直应变转移到水平应变，从而防止形成铜海丘。

    Package structure for a chip and method for fabricating the same
    18.
    发明授权
    Package structure for a chip and method for fabricating the same 有权
    一种芯片的封装结构及其制造方法

    公开(公告)号：US08633558B2

    公开(公告)日：2014-01-21

    申请号：US12981640

    申请日：2010-12-30

    申请人： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

    发明人： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

    IPC分类号： H01L31/0216 ,  H01L31/18

    CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

    摘要翻译： 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。

    Chip package and method for fabricating the same
    20.
    发明授权
    Chip package and method for fabricating the same 有权
    芯片封装及其制造方法

    公开(公告)号：US08207615B2

    公开(公告)日：2012-06-26

    申请号：US13010478

    申请日：2011-01-20

    申请人： Bai-Yao Lou ,  Tsang-Yu Liu ,  Long-Sheng Yeou

    发明人： Bai-Yao Lou ,  Tsang-Yu Liu ,  Long-Sheng Yeou

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/14618 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/1461 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package, which includes a substrate having an upper surface and a lower surface, a chip disposed in or on the substrate, a pad disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer located overlying a sidewall of the hole, and a conducting layer located overlying the insulating layer and electrically connected to the pad.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，设置在基板中或基板上的芯片，设置在基板中或基板上并与芯片电连接的焊盘， 从下表面向上表面露出焊盘，其中靠近下表面的孔的下开口具有比上表面附近的孔的上开口短的宽度，绝缘层位于 孔的侧壁，以及位于绝缘层上方并电连接到焊盘的导电层。