公开(公告)号：US07755389B2

公开(公告)日：2010-07-13

申请号：US12350219

申请日：2009-01-07

Applicant: Colin Neal Murphy ,  Narbeh Derhacobian ,  Louis Charles Kordus, II ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

Inventor： Colin Neal Murphy ,  Narbeh Derhacobian ,  Louis Charles Kordus, II ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

IPC: H03K19/177 ,  G11C11/34

CPC classification number: G11C13/0011 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  G11C23/00 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract translation: 可重构的电子结构和电路使用可编程的非易失性存储元件。 可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件， ）。 可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

公开(公告)号：US20080025080A1

公开(公告)日：2008-01-31

申请号：US11494413

申请日：2006-07-27

Applicant: Vei-Han Chan ,  Louis Kordus ,  Narbeh Derhacobian ,  Jason Golbus

Inventor： Vei-Han Chan ,  Louis Kordus ,  Narbeh Derhacobian ,  Jason Golbus

IPC: G11C11/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078

Abstract: Methods and apparatus for programming a phase change device (PCD) to a low resistance state. According to an exemplary method, one or more first programming pulses having a predetermined magnitude and/or duration are applied to a PCD. After each programming pulse is applied, the programmed resistance of the PCD is compared to a target resistance specification. If the programmed resistance is not in accordance with the target resistance specification, one or more second programming pulses having a magnitude and/or duration different than the magnitude and/or duration of the one or more first programming pulses are applied to the PCD. This process is repeated until the programmed resistance of the PCD satisfies the target resistance specification or it is determined that the PCD cannot be programmed to a resistance value that satisfies the target resistance specification.

Abstract translation: 将相变装置（PCD）编程为低电阻状态的方法和装置。 根据示例性方法，具有预定幅度和/或持续时间的一个或多个第一编程脉冲被施加到PCD。 在应用每个编程脉冲后，将PCD的编程电阻与目标电阻规范进行比较。 如果编程的电阻不符合目标电阻规范，则具有与一个或多个第一编程脉冲的幅度和/或持续时间不同的幅度和/或持续时间的一个或多个第二编程脉冲被施加到PCD。 重复该过程直到PCD的编程电阻满足目标电阻规格或者确定PCD不能被编程为满足目标电阻规格的电阻值。

公开(公告)号：US20070146012A1

公开(公告)日：2007-06-28

申请号：US11267718

申请日：2005-11-03

Applicant: Colin Murphy ,  Narbeh Derhacobian ,  Louis Kordus ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas Stewart

Inventor： Colin Murphy ,  Narbeh Derhacobian ,  Louis Kordus ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas Stewart

IPC: H03K19/00

CPC classification number: G11C13/0011 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  G11C23/00 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract translation: 可重构的电子结构和电路使用可编程的非易失性存储元件。 可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件， ）。 可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

公开(公告)号：US20060008997A1

公开(公告)日：2006-01-12

申请号：US11197562

申请日：2005-08-04

Applicant: Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

Inventor： Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

IPC: H01L21/336

CPC classification number: H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/3162 ,  H01L21/31683 ,  H01L29/40114 ,  H01L29/511

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

公开(公告)号：US06787415B1

公开(公告)日：2004-09-07

申请号：US10402698

申请日：2003-03-28

Applicant: Mei-Hua Chung ,  Ching-Hwa Chen ,  Vei-Han Chan

Inventor： Mei-Hua Chung ,  Ching-Hwa Chen ,  Vei-Han Chan

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of row structures (280). Each row structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the row structures before the conductive layer (160) for the wordlines is deposited. The pedestals are formed in the area of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals raise the top surface of the wordline layer near the contact openings, so the contact opening etch can be made shorter. The pedestals also increase the minimum thickness of the wordline layer near the contact openings, so the loss of the wordline layer during the etch of the contact openings becomes less critical, and the photolithographic tolerances required for patterning the contact openings can be relaxed. The pedestals can be dummy structures (they may have no electrical functionality).

Abstract translation: 非易失性存储字字（160）形成为在行结构（280）的侧壁上的侧壁间隔物。 每个行结构可以包含浮动和控制门（120,140）或一些其它元件。 在放置用于字线的导电层（160）之前，与行结构相邻地形成基座（340）。 基座形成在接触开口（330.1）的将在上覆电介质（310）中被蚀刻以形成与字线的接触的区域中。 基座使接触开口附近的字线层的上表面升高，因此可以使接触开口蚀刻更短。 基座也增加了接触开口附近的字线层的最小厚度，因此在接触开口的蚀刻期间字线层的损失变得不那么关键，并且可以放宽图形化接触开口所需的光刻公差。 基座可以是虚拟结构（它们可能没有电气功能）。

公开(公告)号：US6046932A

公开(公告)日：2000-04-04

申请号：US417273

申请日：1999-10-13

Applicant: Colin Bill ,  Sameer S. Haddad ,  Jonathan Shi-Chang Su ,  Vei-Han Chan

Inventor： Colin Bill ,  Sameer S. Haddad ,  Jonathan Shi-Chang Su ,  Vei-Han Chan

IPC: G11C16/06 ,  G11C16/02 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/12 ,  G11C16/16

CPC classification number: G11C16/3409 ,  G11C16/30 ,  G11C16/3404

Abstract: A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

Abstract translation: 一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。 闪存单元被组织成具有每个块具有列和行的I / O块的阵列。 公共阵列源连接和地之间连接一组电阻。 电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。 当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。 选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

Applicant: Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

Inventor： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US5875130A

公开(公告)日：1999-02-23

申请号：US085705

申请日：1998-05-27

Applicant: Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chan ,  Colin S. Bill

Inventor： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chan ,  Colin S. Bill

IPC: G11C16/10 ,  G11C16/34 ,  G11C13/00

CPC classification number: G11C16/3409 ,  G11C16/10 ,  G11C16/3404

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.

Abstract translation: 闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。 控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值 电池中的漏电流。 操作脉冲可以是过高修正脉冲。 在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。 操作脉冲也可以是编程脉冲。 在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。 偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

公开(公告)号：US08222917B2

公开(公告)日：2012-07-17

申请号：US11591734

申请日：2006-11-02

Applicant: Antonietta Oliva ,  Louis Charles Kordus ,  Vei-Han Chan

Inventor： Antonietta Oliva ,  Louis Charles Kordus ,  Vei-Han Chan

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H04L25/0278 ,  H03H7/38

Abstract: Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between an output of the comparator and the programmable resistance element. The programmable resistance element includes one or more programmable resistance devices (PRDs). Programmed resistances of the programmable resistance element combine with the resistance of an external reference resistor to provide an impedance matched termination. A change in the resistance of the termination impedance causes a change in the output of the comparator. The impedance element control circuit responds to changes in the output of the comparator by providing one or more program control output signals, which control the resistance values of one or more of the PRDs, thereby maintaining an impedance matched termination.

Abstract translation: 使用可编程电阻器件的阻抗匹配和修整设备和方法。 根据一个示例性实施例，阻抗匹配电路包括可编程电阻元件，比较器，具有耦合到比较器的第一输入的公共节点的电阻器分压器，以及耦合在比较器的输出和 可编程电阻元件。 可编程电阻元件包括一个或多个可编程电阻器件（PRD）。 可编程电阻元件的编程电阻与外部参考电阻的电阻相结合，提供阻抗匹配的端接。 端接阻抗的电阻变化导致比较器输出的变化。 阻抗元件控制电路通过提供控制一个或多个PRD的电阻值的一个或多个程序控制输出信号来响应比较器输出的变化，从而保持阻抗匹配的终止。

公开(公告)号：US08183551B2

公开(公告)日：2012-05-22

申请号：US11267788

申请日：2005-11-03

Applicant: Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

Inventor： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

Abstract translation: 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。