公开(公告)号：US20090194887A1

公开(公告)日：2009-08-06

申请号：US12026742

申请日：2008-02-06

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US08421204B2

公开(公告)日：2013-04-16

申请号：US13110865

申请日：2011-05-18

申请人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

发明人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/185 ,  H01L2924/00

摘要： Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding.

摘要翻译： 公开了由嵌入式半导体芯片和电气部件的模块构成的半导体管芯封装。 在一个实施例中，半导体管芯封装包括第一模块和连接到第一模块的第二模块。 一个或多个半导体裸片嵌入在第一模块中，并且一个或多个电组件，例如表面安装组件，嵌入在第二模块中。 第一模块可以通过层压工艺形成，并且第二模块可以通过层压工艺或模制工艺形成。 图案化的金属层和通孔提供对封装以及芯片和封装的部件之间的电互连。 第二模块可以通过将单独制造的模块的互连焊盘彼此连接，或者可以通过层压或模制来直接附接到第一模块。

公开(公告)号：US20120094436A1

公开(公告)日：2012-04-19

申请号：US13276372

申请日：2011-10-19

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L21/60

CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US20090189266A1

公开(公告)日：2009-07-30

申请号：US12020855

申请日：2008-01-28

申请人： Yong Liu ,  William Newberry ,  Margie T. Rios ,  Qiuxiao Qian

发明人： Yong Liu ,  William Newberry ,  Margie T. Rios ,  Qiuxiao Qian

IPC分类号： H01L23/02 ,  H01L21/02

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package.

摘要翻译： 在本说明书中公开了具有堆叠骰子的降压转换器封装和用于形成降压转换器的工艺。 该封装包括一个安装在一个表面上的具有一个低边裸片的芯片安装板和一个安装在相对表面上的高边模具。 芯片焊盘是导电的，使得低边裸片的漏极通过焊盘连接到高侧裸片的源极。 控制器模具控制高低侧模具的门。 多个引线延伸到封装的外部，以允许电连接到封装的内部。 高侧漏极暴露于封装的一个表面。

公开(公告)号：US20120326170A1

公开(公告)日：2012-12-27

申请号：US13166697

申请日：2011-06-22

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L33/48 ,  H01L33/62

CPC分类号： H01L25/167 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00

摘要： Optocoupler packages and methods of making the same. An exemplary package comprises a substrate having a first surface, a second surface opposite the first surface, and a body of electrically insulating material disposed between the first and second surfaces; a first optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces, the first optoelectronic device having a first conductive region and a second conductive region; a second optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces and optically coupled to the first optoelectronic device, the second optoelectronic device having a first conductive region and a second conductive region; and a plurality of electrical traces disposed on one or both surfaces of the substrate and electrically coupled to the conductive regions of the optoelectronic devices.

摘要翻译： 光耦合器封装及其制作方法。 示例性包装包括具有第一表面，与第一表面相对的第二表面的基底和设置在第一和第二表面之间的电绝缘材料体; 第一光电子器件，其嵌入在所述衬底的电绝缘材料的主体中并且设置在所述衬底的第一和第二表面之间，所述第一光电器件具有第一导电区域和第二导电区域; 第二光电子器件，其嵌入在所述衬底的电绝缘材料的主体中并且设置在所述衬底的第一和第二表面之间并且光耦合到所述第一光电子器件，所述第二光电子器件具有第一导电区域和第二导电区域; 以及设置在所述基板的一个或两个表面上并电耦合到所述光电子器件的导电区域的多个电迹线。

公开(公告)号：US08023279B2

公开(公告)日：2011-09-20

申请号：US12404627

申请日：2009-03-16

申请人： Qiuxiao Qian ,  Yong Liu

发明人： Qiuxiao Qian ,  Yong Liu

IPC分类号： H05K1/18

CPC分类号： H05K7/1432 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19107 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00 ,  H01L2224/45099

摘要： An encapsulated buck converter module includes a low side transistor and a control integrated circuit bonded to a first section on a first side of a leadframe, a first clip between a source of the low side transistor and a second section, a source contact of a high side transistor attached to the first section on a second side of the leadframe with a gate contact of the high side transistor attached to a third section, a conductive member attached to the first and second sections on the second side of the leadframe wherein the first side of the conductive member attached to the second conductive member forms a conductive path with a portion of a second side of the conductive member while any portion of the first side of the conductive member attached to the first component attachment section is insulated from the first side of the conductive member, a first plate of a capacitor attached to a drain contact of the high side transistor and a second plate of the capacitor attached to the second side of the conductive member, and means for forming an external connection to the drain contact of the high side transistor.

摘要翻译： 封装的降压转换器模块包括：低侧晶体管和与引线框架的第一侧上的第一部分结合的控制集成电路;在低侧晶体管的源极与第二部分之间的第一夹子， 在所述引线框架的第二侧附接到所述第一部分的侧面晶体管，所述第一部分具有附接到第三部分的所述高侧晶体管的栅极接触;导电部件，其附接到所述引线框架的第二侧上的所述第一和第二部分，其中所述第一侧 连接到第二导电构件的导电构件形成具有导电构件的第二侧的一部分的导电路径，而导电构件的附接至第一构件安装部的第一侧的任何部分与第一构件附接部的第一侧绝缘 导电构件，附接到高侧晶体管的漏极接触的电容器的第一板和连接到s的电容器的第二板 导电部件的漏极侧，以及用于与高侧晶体管的漏极接触形成外部连接的装置。

公开(公告)号：US08018054B2

公开(公告)日：2011-09-13

申请号：US12046939

申请日：2008-03-12

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/34

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes a first semiconductor die attached the first die attach pad at the first side of the leadframe structure, and a second semiconductor die attached to the second die attach pad at the second side of the leadframe structure. The semiconductor die package further includes a housing material covering at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die.

摘要翻译： 半导体管芯封装。 半导体管芯封装包括引线框结构，其包括第一管芯附接焊盘和与第一管芯附接焊盘横向间隔开的第二管芯附接焊盘，第一侧和与第一侧相对的第二侧。 所述半导体管芯封装还包括第一半导体管芯，所述第一半导体管芯在所述引线框架结构的第一侧附接所述第一管芯附着焊盘，以及在所述引线框架结构的第二侧附接到所述第二管芯附接焊盘的第二半导体管芯。 半导体管芯封装还包括覆盖引线框结构，第一半导体管芯和第二半导体管芯的至少一部分的壳体材料。

公开(公告)号：US07768123B2

公开(公告)日：2010-08-03

申请号：US11861967

申请日：2007-09-26

申请人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian ,  Jianhong Ju

发明人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian ,  Jianhong Ju

IPC分类号： H01L23/34

CPC分类号： H01L24/06 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/39 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37599 ,  H01L2224/45014 ,  H01L2224/45139 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2224/37099

摘要： A semiconductor die package. It includes a substrate having a first surface and a second surface, a first semiconductor die having its front surface facing the first surface of the substrate, a conductive adhesive disposed between the first semiconductor die and the first surface of the substrate, and a second semiconductor die located on the first semiconductor die. The front surface of second semiconductor die faces away from the first semiconductor die, and the back surface faces toward the first semiconductor die. A plurality of conductive structures electrically couple regions at the front surface of the second semiconductor die to conductive regions at the first surface of the substrate.

摘要翻译： 半导体管芯封装。 它包括具有第一表面和第二表面的衬底，第一半导体管芯，其前表面面向衬底的第一表面，设置在第一半导体管芯和衬底的第一表面之间的导电粘合剂，以及第二半导体 位于第一半导体管芯上。 第二半导体管芯的前表面远离第一半导体管芯，并且后表面朝向第一半导体管芯。 多个导电结构将第二半导体管芯的前表面处的区域电耦合到衬底的第一表面处的导电区域。

公开(公告)号：US07750445B2

公开(公告)日：2010-07-06

申请号：US11857199

申请日：2007-09-18

申请人： Yong Liu ,  Qiuxiao Qian ,  Honorio T. Granada, Jr.

发明人： Yong Liu ,  Qiuxiao Qian ,  Honorio T. Granada, Jr.

IPC分类号： H01L23/495

CPC分类号： H02M7/003 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/00

摘要： A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.

摘要翻译： 多片模块降压转换器10具有在两个mosfet之间的高侧功率MOSFET 12，低侧功率mosfet 22和预成型引线框40，用于将mosfet源12连接到mosfet 22的漏极。 18和26从平行但间隔开的平面的平面上携带mosfet的源极，栅极和漏极端子。

公开(公告)号：US20090072359A1

公开(公告)日：2009-03-19

申请号：US11857199

申请日：2007-09-18

申请人： Yong Liu ,  Qiuxiao Qian ,  Honorio T. Granada, JR.

发明人： Yong Liu ,  Qiuxiao Qian ,  Honorio T. Granada, JR.

IPC分类号： G05F1/44 ,  B23P19/04

CPC分类号： H02M7/003 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/00

摘要： A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.

摘要翻译： 多片模块降压转换器10具有在两个mosfet之间的高侧功率MOSFET 12，低侧功率mosfet 22和预成型引线框40，用于将mosfet源12连接到mosfet 22的漏极。 18和26从平行但间隔开的平面的平面上携带mosfet的源极，栅极和漏极端子。