公开(公告)号：US07932148B2

公开(公告)日：2011-04-26

申请号：US12378040

申请日：2009-02-09

申请人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

发明人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/76232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。 圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。 圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

公开(公告)号：US07851286B2

公开(公告)日：2010-12-14

申请号：US12456949

申请日：2009-06-25

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L21/336

CPC分类号： H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： This invention discloses a method to form a bottom-source lateral diffusion MOS (BS-LDMOS) device with a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The method includes a step of applying a sinker-channel mask for carrying out a deep sinker multiple energy implant to form a combined sinker-channel region in lower portion of an epitaxial layer to function as a buried source-body contact extending to and contacting a bottom of the substrate functioning as a bottom source electrode.

摘要翻译： 本发明公开了一种形成底源横向扩散MOS（BS-LDMOS）器件的方法，源极区域设置在半导体衬底的顶表面附近的漏极区域的横向相对的位置，该半导体衬底在源极区域和漏极区域之间支撑栅极 。 该方法包括以下步骤：施加沉降通道掩模，用于进行深沉沉多次能量注入，以在外延层的下部形成组合沉降沟道区，以用作延伸到和接触的外部源体接触 底部的底部用作底部源极。

公开(公告)号：US07824977B2

公开(公告)日：2010-11-02

申请号：US11729408

申请日：2007-03-27

申请人： YongZhong Hu ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Sung-Shan Tai

IPC分类号： H01L29/00

CPC分类号： H01L29/7322 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

摘要： A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

摘要翻译： 半导体晶片包括至少部分制造的由高压低电压去耦层覆盖的高压晶体管和至少部分制造的低压晶体管，其中蚀刻掉高压低压去耦层， 电压制造工艺。 包括约30-150埃的高温氧化物（HTO）氧化物层和低压化学气相沉积（LPCVD）氮化物层的高压低电压去耦层。

公开(公告)号：US07805687B2

公开(公告)日：2010-09-28

申请号：US11541369

申请日：2006-09-30

申请人： YongZhong Hu ,  Yu Cheng Chang ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Yu Cheng Chang ,  Sung-Shan Tai

IPC分类号： G06F17/50

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.

摘要翻译： 在本发明中公开了执行编程，测试和修整操作的方法。 该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率 实现了存储单元。 将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。 这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。 编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

公开(公告)号：US07799646B2

公开(公告)日：2010-09-21

申请号：US12098970

申请日：2008-04-07

申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。 主FET和一个或多个感测FET形成在公共衬底中。 主FET和每个感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。 在主FET和一个或多个感测FET的栅极端子之间设置电隔离。 本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

公开(公告)号：US07786531B2

公开(公告)日：2010-08-31

申请号：US11182918

申请日：2005-07-14

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/7803 ,  H01L29/945 ,  H01L2223/6644 ,  H03K17/165

摘要： This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

摘要翻译： 本发明公开了一种新的沟槽垂直半导体功率器件，其包括形成在覆盖在沟槽栅极顶部的介电层之间的导电层之间的电容器。 在具体实施例中，沟槽垂直半导体功率器件可以是沟槽金属氧化物半导体场效应晶体管（MOSFET）功率器件。 沟槽栅极是沟槽多晶硅栅极，并且导电层是覆盖设置在沟槽多晶硅栅极顶部的多晶硅介电层的第二多晶硅层。 导电层还连接到垂直功率器件的源极。

公开(公告)号：US20090294934A1

公开(公告)日：2009-12-03

申请号：US12130663

申请日：2008-05-30

申请人： Lei Shi ,  Kai Liu ,  Ming Sun

发明人： Lei Shi ,  Kai Liu ,  Ming Sun

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49524 ,  H01L23/4334 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/544 ,  H01L24/28 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers.

摘要翻译： 用于半导体器件封装的夹子可以包括通过一个或多个导电桥彼此电连接的两个或更多个分离的导电指状物。 至少手指的第一端适于与引线框架电接触。 桥适于提供与半导体器件的顶部半导体区域的电连接，并且还可以在手指的顶表面暴露时提供散热路径。 半导体器件封装可以包括夹子以及半导体器件和引线框架。 半导体器件可以分别在顶表面和底表面上具有第一半导体区域和半导体区域。 夹子可以在桥接处电连接到顶部半导体区域，并且在至少一个手指的第一端处电连接到引线框架。

公开(公告)号：US20090261883A1

公开(公告)日：2009-10-22

申请号：US12456948

申请日：2009-06-25

申请人： Madhur Bobde

发明人： Madhur Bobde

IPC分类号： H03K5/08 ,  H01S4/00

CPC分类号： H01L27/0259 ,  Y10T29/49002

摘要： A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

摘要翻译： 用于抑制瞬态电压的对称阻塞瞬态电压抑制（TVS）电路包括具有电连接到两个晶体管的公共源的基极的NPN晶体管，由此基极连接到正或负的低电位的端子 电压瞬变。 两个晶体管是用于实现基本上对称的双向钳位瞬态电压的两个基本相同的晶体管。 这两个晶体管还包括具有电互连源的第一和第二MOSFET晶体管。 第一MOSFET晶体管还包括连接到高电位端子的漏极和连接到低电位端子的栅极，并且第二MOSFET晶体管还包括连接到低电位端子的端子的漏极和连接到高电位的栅极 潜在终端。

公开(公告)号：US07602029B2

公开(公告)日：2009-10-13

申请号：US11518001

申请日：2006-09-07

申请人： Shekar Mallikararjunaswamy

发明人： Shekar Mallikararjunaswamy

IPC分类号： H01L29/72

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558

摘要： This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a single polysilicon stripe functioning as a gate wherein the OTP memory further includes a drift region for counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region. In a preferred embodiment, the first and second MOS transistors are N-MOS transistors disposed in a common P-well and the drift region of the first MOS transistor further comprising a P-drift region.

摘要翻译： 本发明公开了一种可编程（OTP）存储器。 OTP存储器包括并联连接并由用作栅极的单个多晶硅条纹控制的第一和第二金属氧化物半导体（MOS）晶体管，其中OTP存储器还包括漂移区域，用于反向掺杂包含着色层的轻掺杂漏极（LDD） 并且围绕具有与漂移区域未到达的第二MOS晶体管不同的阈值电压的第一MOS晶体管的漏极和源极。 在优选实施例中，第一和第二MOS晶体管是N沟道MOS晶体管，其设置在公共P阱中，并且第一MOS晶体管的漂移区域还包括P漂移区域。

公开(公告)号：US20090219044A1

公开(公告)日：2009-09-03

申请号：US12454004

申请日：2009-05-11

申请人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

发明人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： H04L63/102 ,  G01R31/2625 ,  G01R31/2884 ,  G01R35/005 ,  H01L22/14 ,  H01L2924/0002 ,  H04L63/08 ,  H01L2924/00

摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

摘要翻译： 本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。 该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。