公开(公告)号：US3810795A

公开(公告)日：1974-05-14

申请号：US26786072

申请日：1972-06-30

申请人： IBM

发明人： TROUTMAN R

IPC分类号： H01L27/04 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/339 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/148 ,  H01L29/00 ,  H01L29/417 ,  H01L29/49 ,  H01L29/762 ,  H01L7/34

CPC分类号： H01L29/4983 ,  H01L21/00 ,  H01L21/823406 ,  H01L23/485 ,  H01L23/522 ,  H01L27/148 ,  H01L29/00 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10S438/934 ,  H01L2924/00

摘要： ANOTHER IN SELECTED AREAS. CRITICAL ALIGNMENTS BETWEEN MASKS AND SUBSEQUENT DIFFUSIONS ARE VOIDED. THE METHOD OF THE INVENTION MAY BE USED TO CREATE ALL TYPES OF SEMICONDUCTOR DEVICES, ESPECIALLY FIELD EFFECT TRANSISTORS AND CHARGE-COUPLED DEVICES EITHER SEPARATELY OR SIMULTANEOUSLY ON THE SAME BODY.

INTERCONNECTED, BUT SELF-ISOLATING CONDUCTIVE LINES ON DIFFERENT LEVELS ARE ACHIEVED ON MONOLITHIC INTEGRATED SEMICONDUCTOR DEVICES. LAYERS OF INSULATING SEMICONDUCTORS MATERIAL ARE SEPARATED IN SELECTED AREAD BY DEPOSITS OF A DIELECTRIC DIFFUSION BARRIER MATERIAL AND DOPANTS TO RENDER THE LAYERS CONDUCTIVE ARE DIFFUSED THEREIN. THE DEPOSITS OF THE BURIED BARRIER MATERIAL ACT AS A DIFFUSION MASK AS TO PREVENT THE DIFFUSED DOPANTS FROM PENETRATING INTO SELECTED AREAS OF THE UNDERLYING SEMICONDUCTIVE LAYER A NON-CONLEAVE IN THE UNDERLYING SEMICONDUCTOR LAYERS A NON-CONDUCTIVE REGION. THIS CAUSES PORTIONS OF THE LAYERS OF INSULATING MATERIAL TO BE RENDERED CONDUCTIVE, WHILE STILL MAINTAINING THEIR INSULATING CHARACTERISTICS IN SELECTED REGIONS, THEREBY ELECTRICALLY SEPARATING THE LAYERS ONE FORM

公开(公告)号：US09929155B2

公开(公告)日：2018-03-27

申请号：US14985385

申请日：2015-12-30

申请人： Ju-youn Kim ,  Jong-mil Youn

发明人： Ju-youn Kim ,  Jong-mil Youn

IPC分类号： H01L27/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/823406 ,  H01L21/823431 ,  H01L29/0684 ,  H01L29/785 ,  H01L29/7854

摘要： A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly scaled integrated circuit device. The semiconductor device includes a first active fin unit protruding on a first region of a semiconductor substrate and extending along a first direction. The first active fin unit includes at least one first active fin having left and right profiles, which are symmetric to each other about a first center line perpendicular to a top surface of the semiconductor substrate on a cut surface perpendicular to the first direction. A second active fin unit protrudes on a second region of the semiconductor substrate and includes two second active fins, each having a left and right profiles, which are asymmetric to each other about a second center line perpendicular to the top surface of the semiconductor substrate on a cut surface.

公开(公告)号：US20160322422A1

公开(公告)日：2016-11-03

申请号：US15107977

申请日：2014-12-11

申请人： SONY CORPORATION

发明人： TAKASHI YOKOYAMA ,  TAKU UMEBAYASHI

IPC分类号： H01L27/22 ,  H01L29/04 ,  H01L29/768 ,  H01L43/02 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L27/228 ,  H01L21/823406 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/045 ,  H01L29/42396 ,  H01L29/768 ,  H01L29/7827 ,  H01L29/7843 ,  H01L29/7846 ,  H01L43/02

摘要： A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

摘要翻译： 该技术的半导体器件包括第一扩散部分（22），第二扩散部分（21），通道部分（23），栅极部分（24）和应力施加部分（31,32或33） 。 在具有槽（10A）的半导体层（10）中，第一扩散部（22）形成在槽（10A）的底部或其附近，第二扩散部（21）形成在上部 沟槽部分（23）形成在第一扩散部分（22）和第二扩散部分（21）之间。 栅极部分（24）在与沟道部分（23）相对的位置处埋在槽（10A）中。 应力施加部（31,32,33）在向半导体层（10）的法线方向向通道部（23）施加压缩应力和拉伸应力。

公开(公告)号：US06841811B2

公开(公告)日：2005-01-11

申请号：US10641640

申请日：2003-08-14

申请人： David Wen ,  Steve Onishi

发明人： David Wen ,  Steve Onishi

IPC分类号： H01L21/8234 ,  H01L27/146 ,  H01L27/148

CPC分类号： H01L21/823406 ,  H01L27/14687 ,  H01L27/14843

摘要： Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

摘要翻译： 提供大面积，快速帧速率，电荷耦合器件（CCD）。 行间传输CCD可以具有交错的钉扎光电二极管和垂直移位寄存器。 线间传输CCD是从连续光源产生高帧率视频图像的理想选择。 光电二极管将指示先前视频帧的电荷传输到具有很小或没有滞后的相邻垂直移位寄存器，而来自当前视频帧的光则集成在光电二极管中。 充电信号仅需要从光电二极管行进到相邻的垂直移位寄存器。 指示每个视频帧的电荷信号然后被移出垂直移位寄存器。 每个垂直移位寄存器具有增加电荷转移速率的掺杂梯度。 所有这些因素即使在大面积CCD中也能提供快速高效的视频帧率。

公开(公告)号：US4877754A

公开(公告)日：1989-10-31

申请号：US173003

申请日：1988-03-31

申请人： Hermanus L. Peek

发明人： Hermanus L. Peek

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L21/8234 ,  H01L27/148

CPC分类号： H01L29/66954 ,  H01L21/823406 ,  Y10S257/90

摘要： A semiconductor device comprising a semiconductor body (1) having a surface (2) provided with a first insulating layer (3). On this layer is disposed a pattern of conductor strips (4) coated with insulation strips (5) with projecting edges (6). Under the edges (6), the conductor strips (4) are coated with insulating tracks (8) which fill the spaces under the edges (6) and which at least at the area where they adjoin the first insulating layer (3) can be etched selectively with respect to this layer (3). As a material for the conductor strips (4) use may be made of materials other than polycrystalline silicon, such as tungsten, molybdenum and silicides. The thickness of the first insulating layer (3) is affected to a very small extent during the manufacture of the device, while its depth remains unchanged.

公开(公告)号：US4461070A

公开(公告)日：1984-07-24

申请号：US382878

申请日：1982-05-28

申请人： Harvey E. Cline

发明人： Harvey E. Cline

IPC分类号： H01L21/339 ,  H01L21/8234 ,  H01L27/10

CPC分类号： H01L29/66954 ,  H01L21/823406 ,  Y10T428/12465

摘要： A method is described for the fabrication of charge-coupled devices by the formation of a thin film lamellar metallic eutectic and subsequent selective removal of one of the eutectic phases to form one of the spaced gate arrays of such devices.

摘要翻译： 描述了通过形成薄膜层状金属共晶体并随后选择性地去除其中一个共晶相以形成这种器件的间隔开的栅极阵列之一来制造电荷耦合器件的方法。

公开(公告)号：US4352237A

公开(公告)日：1982-10-05

申请号：US187773

申请日：1980-09-16

申请人： Dietrich Widmann

发明人： Dietrich Widmann

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/283

CPC分类号： H01L29/66954 ,  H01L21/823406 ,  Y10S438/911

摘要： In an exemplary embodiment, after underetching a first polysilicon layer beneath spaced SiO.sub.2 cover layers to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO.sub.2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO.sub.2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO.sub.2 overhangs may have an extent (e.g. 0.7 microns) about equal to the electrode layer thickness (e.g. 0.8 microns).

摘要翻译： 在一个示例性实施例中，在将第二多晶硅层放置在间隔开的SiO 2覆盖层之下以产生成对的相对间隔的间隔开的SiO 2悬垂线之后，并且在由第一多晶硅形成的间隔开的多晶Si-1电极的端面处提供绝缘层 层，通过化学气相沉积（CVD）产生第二多晶硅层，以便通过每对相对的突出端之间的间隙填充SiO 2悬垂体下方的空腔。 然后蚀刻掉第二多晶硅层，以便留下由第二多晶硅层形成的介入的自调节的非重叠的多晶硅二极管，其表面终止于例如稍微低于SiO 2覆盖层的上表面。 对于六微米的多晶Si-1电极的中心到中心间隔，SiO 2悬垂部分可以具有等于电极层厚度（例如0.8微米）的程度（例如0.7微米）。

公开(公告)号：US4229752A

公开(公告)日：1980-10-21

申请号：US906385

申请日：1978-05-16

申请人： Jaroslav Hynecek

发明人： Jaroslav Hynecek

IPC分类号： H01L29/762 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8234 ,  H01L27/148 ,  H01L29/423 ,  H01L29/76 ,  H01L29/768 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/66954 ,  G11C19/282 ,  G11C27/04 ,  H01L21/823406 ,  H01L27/148 ,  H01L29/42396 ,  H01L29/76833 ,  H01L29/76866

摘要： A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II (.phi..sub.max II) remains greater than for region I (.phi..sub.max I) and .phi..sub.max IV>.phi..sub.max III, for both gate conditions. A self-aligned process for fabrication is provided, including a number of ion implant stages to fix the required impurity profiles in each cell for generating the correct potential profiles for charge propagation. CCD imagers, memory devices, an analog processors are contemplated systems wherein the invention is to be implemented.

摘要翻译： 一种单相埋入通道的半导体电荷转移装置，其中每个单元的一部分包括反型层或半导体表面处的“虚拟电极”，屏蔽该区域不受任何栅极引起的电位变化。 每个单元由四个区域（I，II，III，IV）组成，其中每个区域的特征杂质分布决定了栅极“导通”和栅极“关闭”条件下产生的最大电位。 对门进行时钟导致区域I和II中的电位最大值在虚拟电极下方的区域III和IV中的固定电位最大值之上和之下循环。 由此实现电荷转移的方向性，因为对于两个栅极条件，区域II（phi maxII）的电势最大值保持大于区域I（phi maxI）和phi maxIV> phi maxIII。 提供了一种用于制造的自对准工艺，其包括多个离子注入阶段，以在每个单元中固定所需的杂质分布，以产生用于电荷传播的正确的电位分布。 CCD成像器，存储器件，模拟处理器是其中将实现本发明的预期系统。

公开(公告)号：US4133099A

公开(公告)日：1979-01-09

申请号：US821183

申请日：1977-08-02

申请人： Yoshiaki Hagiwara

发明人： Yoshiaki Hagiwara

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/339 ,  H01L21/8234 ,  H01L27/148 ,  H01L29/10 ,  H01L29/762 ,  B01J17/00

CPC分类号： H01L29/66954 ,  H01L21/033 ,  H01L21/823406 ,  H01L29/1062

摘要： A method of manufacturing charge transfer devices in which an asymmetrical potential well in the direction of charge transfer is formed by the shape of narrower portions of a transfer channel which is bordered by highly doped channel stoppers. Impurities are diffused through a first mask into a polycrystalline silicon layer on the surface of a semiconductor substrate to construct transfer electrodes of highly doped polycrystalline layer. Then impurities are diffused into a semiconductor substrate through openings bordering on one edge with a first mask to form the highly doped portions to make the narrower portions of the transfer channel to assure that the edges of the transfer electrode and the edge of the narrower portion are aligned.

摘要翻译： 一种制造电荷转移装置的方法，其中电荷转移方向上的非对称势阱通过由高掺杂通道阻挡物界定的转移通道的较窄部分的形状形成。 杂质通过第一掩模扩散到半导体衬底的表面上的多晶硅层中以构成高掺杂多晶层的转移电极。 然后杂质通过与一个边缘邻接的开口与第一掩模扩散到半导体衬底中，以形成高掺杂部分，以形成传输沟道的较窄部分，以确保转移电极的边缘和较窄部分的边缘为 对齐

公开(公告)号：US4077112A

公开(公告)日：1978-03-07

申请号：US749336

申请日：1976-12-10

申请人： Matthias Johannes Joseph Theunissen ,  Roelof Pieter Kramer ,  Hermanus Leonardus Peek

发明人： Matthias Johannes Joseph Theunissen ,  Roelof Pieter Kramer ,  Hermanus Leonardus Peek

IPC分类号： H01L21/28 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/768 ,  B01J17/00

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66954 ,  H01L29/76833 ,  Y10S148/114 ,  Y10S438/981

摘要： The invention relates to a charge transfer device (C.T.D.) with polycrystalline silicon electrodes which are provided on a nitride layer. The nitride layer has apertures between the polyelectrodes. Electrodes of a second metallization layer, for example, of aluminium, are provided via said apertures. The charge storage capacities per surface unit (and with equal voltages) can be made equal by subjecting the device for a short period of time to an oxidation treatment prior to providing the Al electrodes so that the oxide layer in the apertures can become thicker than below the Si electrodes.

摘要翻译： 本发明涉及一种具有多晶硅电极的电荷转移装置（C.T.D.），其设置在氮化物层上。 氮化物层在聚电极之间具有孔。 通过所述孔提供第二金属化层的电极，例如铝。 通过在提供Al电极之前使器件经受短时间的氧化处理，使每个表面单元（和相等的电压）的电荷存储容量相等，使得孔中的氧化物层可以变得比下面更厚 Si电极。