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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110095404A1

    公开(公告)日：2011-04-28

    申请号：US12877149

    申请日：2010-09-08

    申请人： Takaharu YAMANO ,  Syota Miki

    发明人： Takaharu YAMANO ,  Syota Miki

    IPC分类号： H01L23/552 ,  H01L21/78

    CPC分类号： H01L23/552 ,  H01L21/3046 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/556 ,  H01L2224/13 ,  H01L2924/3025

    摘要： A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal.

    摘要翻译： 所公开的半导体器件包括：在半导体芯片的电路形成面上具有电极焊盘的半导体芯片，形成在电极焊盘上的内部连接端子，沿半导体芯片的电路形成面的外缘部分形成的台阶部 形成在所述半导体芯片的电路形成面上的第一绝缘层，至少覆盖所述台阶部，形成在所述半导体芯片的电路形成面上以覆盖所述第一绝缘层的第二绝缘层，以及形成在所述第二绝缘层上的互连 第二绝缘层，并且经由内部连接端子电连接到电极焊盘。

    Semiconductor device and its manufacturing method
    12.
    发明授权
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：US07919843B2

    公开(公告)日：2011-04-05

    申请号：US12489577

    申请日：2009-06-23

    申请人： Takaharu Yamano

    发明人： Takaharu Yamano

    IPC分类号： H01L23/02

    CPC分类号： H01L23/522 ,  H01L23/3114 ,  H01L23/552 ,  H01L23/556 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13021 ,  H01L2224/94 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2224/11

    摘要： There is provided a semiconductor device 10 including a solder resist 16 for protecting a wiring pattern 14 electrically connected to a semiconductor chip 11 via an internal connection terminal 12, characterized in that the solder resist 16 is arranged to cover the upper surface of the portion of the wiring pattern 14 not corresponding to the arrangement region of the external connection terminal 17 and the side surface 14B of the wiring pattern 14 and that the area of the solder resist 16 assumed when the upper surface 13A of an insulation layer 13 is viewed from above is substantially the same as that of the wiring pattern 14 assumed when the upper surface 13A of the insulation layer 13 is viewed from above.

    摘要翻译： 提供了一种半导体器件10，其包括用于保护经由内部连接端子12电连接到半导体芯片11的布线图案14的阻焊剂16，其特征在于，阻焊剂16布置成覆盖部分的上表面 布线图案14不对应于外部连接端子17的布置区域和布线图案14的侧面14B，并且当从上方观察绝缘层13的上表面13A时假定阻焊层16的面积 与当从上方观察绝缘层13的上表面13A时假设的布线图案14基本相同。

    COSMIC RAY DETECTORS FOR INTEGRATED CIRCUIT CHIPS
    16.
    发明申请
    COSMIC RAY DETECTORS FOR INTEGRATED CIRCUIT CHIPS 审中-公开
    用于集成电路卡的COSMIC RAY检测器

    公开(公告)号：US20090057565A1

    公开(公告)日：2009-03-05

    申请号：US11936636

    申请日：2007-11-07

    申请人： Eric C. Hannah

    发明人： Eric C. Hannah

    IPC分类号： G01T1/24 ,  G01T1/178

    CPC分类号： G06F11/1405 ,  H01L23/556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A cosmic ray detector includes a cantilever with a first tip. The detector also includes a second tip and circuitry to provide a signal indicative of a distance between the first and second tips being such as would be caused by a cosmic ray interaction event.

    摘要翻译： 宇宙射线检测器包括具有第一尖端的悬臂。 检测器还包括第二尖端和提供指示第一和第二尖端之间的距离的信号的电路，其将由宇宙射线相互作用事件引起。

    Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size
    17.
    发明授权
    Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size 有权
    用于优化时钟速率和最小化芯片尺寸的耐Alpha半导体芯片系统，器件，组件和方法

    公开(公告)号：US07451418B2

    公开(公告)日：2008-11-11

    申请号：US11523247

    申请日：2006-09-19

    申请人： Howard L. Porter ,  Richard S. Rodgers ,  Troy Frerichs

    发明人： Howard L. Porter ,  Richard S. Rodgers ,  Troy Frerichs

    IPC分类号： G06F17/50

    CPC分类号： H01L23/556 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

    摘要： Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be exposed to radiation and the distance between a storage component and a local clock buffer. The radiation, for instance, may be alpha particle radiation emitted from lead (Pb) isotopes in solder bumps formed on the integrated circuit die. The distance, spatial positioning and/or physical proximity of a selected local clock buffer and a storage component are preferably selected so that the skew between the storage component and the local clock buffer is about 30 picoseconds or less. Other maximum skews may be employed, however, such as about 100 picoseconds or less, about 90 picoseconds or less, about 80 picoseconds or less, about 70 picoseconds or less, about 60 picoseconds or less, about 50 picoseconds or less, about 40 picoseconds or less, about 20 picoseconds or less, about 10 picoseconds or less and about 5 picoseconds or less.

    摘要翻译： 本文公开了用于在集成电路管芯上确定在设计阶段中表示半导体部件的存储和非存储单元或组件的放置的系统和方法。 在一个实施例中，相对于要暴露于辐射的区域的敏感性以及存储部件和本地时钟缓冲器之间的距离来分析半导体管芯的区域。 例如，辐射可以是在集成电路芯片上形成的焊料凸块中从铅（Pb）同位素发射的α粒子辐射。 优选地选择所选择的本地时钟缓冲器和存储部件的距离，空间定位和/或物理接近度，使得存储部件和本地时钟缓冲器之间的偏斜大约为30皮秒或更少。 然而，可以使用其他最大偏斜度，例如约100皮秒或更少，约90皮秒或更少，约80皮秒或更少，约70皮秒或更少，约60皮秒或更少，约50皮秒或更少，约40皮秒 或更少，约20皮秒或更少，约10皮秒或更低和约5皮秒或更少。

    Radiation-hardened transistor and integrated circuit
    19.
    发明授权
    Radiation-hardened transistor and integrated circuit 有权
    辐射硬化晶体管和集成电路

    公开(公告)号：US07298010B1

    公开(公告)日：2007-11-20

    申请号：US11358391

    申请日：2006-02-21

    申请人： Kwok K. Ma

    发明人： Kwok K. Ma

    IPC分类号： H01L23/62

    CPC分类号： H01L23/556 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K19/00338 ,  H01L2924/00

    摘要： A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

    摘要翻译： 公开了用于辐射硬化形成在SOI或体半导体衬底上的CMOS IC的复合晶体管。 复合晶体管具有与公共栅极连接串联的电路晶体管和阻塞晶体管。 阻塞晶体管的主体端子仅连接到其源极端子，而不连接到其它连接点。 阻塞晶体管用于防止在电路晶体管中发生的单事件瞬态（SET）耦合到复合晶体管外部。 类似地，当在阻塞晶体管中发生SET时，电路晶体管防止SET耦合到复合晶体管的外部。 可以使用CMOS IC中的每个晶体管的N型和P型复合晶体管来辐射硬化IC，并且可以用于形成作为CMOS IC的构建块的反相器和传输门。