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622 条记录 (耗时 0.07 秒)

    Integrated sensor with frame memory and programmable resolution for light adaptive imaging
    11.
    发明授权
    Integrated sensor with frame memory and programmable resolution for light adaptive imaging 失效
    具有帧存储器和可编程分辨率的集成传感器，用于光自适应成像

    公开(公告)号：US5909026A

    公开(公告)日：1999-06-01

    申请号：US867835

    申请日：1997-06-03

    申请人： Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

    发明人： Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

    IPC分类号： G11C27/04 ,  H04N5/347 ,  H04N5/365 ,  H04N5/369 ,  H04N5/374 ,  H01J40/14

    CPC分类号： H04N5/347 ,  G11C27/04 ,  H04N5/3743

    摘要： An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

    摘要翻译： 一种图像传感器，其可操作以根据接收的光电平改变输出空间分辨率，同时保持期望的信噪比。 添加具有可调整尺寸的像素补丁中的相邻像素的信号以增加图像亮度和信噪比。 一个实施例包括用于接收输入信号的传感器阵列，用于临时存储全帧的帧存储器阵列，以及用于统一的列并行信号求和的自校准列积分器的阵列。 列积分器能够基本上消除固定模式噪声。

    Low noise high performance charge detection system
    12.
    发明授权
    Low noise high performance charge detection system 失效
    低噪声高性能充电检测系统

    公开(公告)号：US5726710A

    公开(公告)日：1998-03-10

    申请号：US538306

    申请日：1995-10-03

    申请人： Jaroslav Hynecek

    发明人： Jaroslav Hynecek

    IPC分类号： H01L29/762 ,  G11C27/04 ,  H01L21/339 ,  H04N5/335 ,  H04N3/14

    CPC分类号： H04N3/1575 ,  G11C27/04

    摘要： The charge coupled device (CCD) charge detection system includes a first CCD register having N non-destructive charge readouts where N is an integer greater than one, and N second CCD registers coupled to the N non-destructive charge readouts where each of the N second CCD registers is coupled to a corresponding one of the N non-destructive charge readouts.

    摘要翻译： 电荷耦合器件（CCD）电荷检测系统包括具有N个非破坏性电荷读数的第一CCD寄存器，其中N是大于1的整数，N个第二CCD寄存器耦合到N个非破坏性电荷读数，其中N个 第二CCD寄存器耦合到N个非破坏性电荷读出中的对应的一个。

    Delay circuit having a plurality of memory cells and corresponding control circuits for controlling the movement of a signal through the memory cells
    13.
    发明授权
    Delay circuit having a plurality of memory cells and corresponding control circuits for controlling the movement of a signal through the memory cells 失效

    公开(公告)号：US5661679A

    公开(公告)日：1997-08-26

    申请号：US595090

    申请日：1996-02-01

    申请人： Sonke Struck

    发明人： Sonke Struck

    IPC分类号： G11C27/04 ,  H03H11/26 ,  G11C7/00 ,  G11C11/24

    CPC分类号： G11C27/04

    摘要： A delay circuit having at least two memory cells (3, 4, 5, 6, 8, 9) each including a capacitive memory element (20, 26, 40, 45), a write transistor (22, 28, 42, 47) by which information to be delayed can be written from a write line (18) into the capacitive memory element (20, 26, 40, 45), and a read transistor (21, 27, 41, 46) by which information can be read from the capacitive memory element (20, 26, 40, 45) on a read line (19), and having a control arrangement which is clocked by means of a first control clock and whose input receives a control signal and which includes intercoupled control circuits (11, 12, 13, 14, 15, 16) one of which is associated with a respective memory cell (3, 4, 5, 6, 8, 9), each control circuit (11, 12, 13, 14, 15, 16) of the read transistor (21, 27, 41, 46) of the associated memory cell (3, 4, 5, 6, 8, 9) being controllable by means of the input signal and each control circuit (11, 12, 13, 14, 15, 16) of the write transistor (22, 28, 42, 47) of the associated memory cell being controllable by means of the output signal, in which each control circuit (11, 12, 13, 14, 15, 16) has a first control element (43, 48, 24, 30) and a subsequent second control element (44, 49, 25, 31), those control circuits (14) whose preceding control circuit (11) is arranged locally remote have a third control element (29) preceding the first control element (30), in that the input of the third control element (29) receives the output signal of the first control element (24) of the preceding, spatially remote control circuit (11), and in that the first control elements (43, 48, 24, 30) of the control circuits (11, 12, 13, 14, 15, 16) are clocked by the first clock and the second (44, 49, 25, 31) and third (29) control elements of the control circuits (11, 12, 13, 14, 15, 16) are clocked by a second clock.

    Charge transfer apparatus with output gate and driving method thereof
    16.
    发明授权
    Charge transfer apparatus with output gate and driving method thereof 失效
    具有输出门的电荷转移装置及其驱动方法

    公开(公告)号：US5615242A

    公开(公告)日：1997-03-25

    申请号：US616284

    申请日：1996-03-15

    申请人： Isao Hirota

    发明人： Isao Hirota

    IPC分类号： H01L29/762 ,  G11C27/04 ,  H01L21/339 ,  H01L27/148 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/369 ,  H04N5/372 ,  G11C19/28 ,  H01L29/768

    CPC分类号： G11C27/04

    摘要： A charge transfer apparatus which is capable of reliably improving the transfer efficiency of an output gate section while preventing the occurrence of coupling to output waveforms. A two-phase driving-type charge transfer apparatus is constructed as follows. Transfer clock .phi.H2 used for driving the stage one prior to the final stage of a charge transfer section is divided at a predetermined ratio through the use of two resistors. This causes the generation of drive pulse .phi.OG in phase with and of a smaller amplitude than transfer clock .phi.H2. A gate electrode of an output gate section is driven by this drive pulse .phi.OG.

    摘要翻译： 一种电荷传送装置，其能够可靠地提高输出栅极部的传输效率，同时防止耦合到输出波形的发生。 二相驱动型电荷转移装置如下构成。 用于在电荷转移部分的最后阶段之前驱动一级的转换时钟phi H2通过使用两个电阻器以预定比例被分配。 这导致与传输时钟phi H2相比并且具有较小振幅的驱动脉冲phi OG的产生。 输出门极部分的栅电极由该​​驱动脉冲phi OG驱动。

    Electronic device with feedback loop
    18.
    发明授权
    Electronic device with feedback loop 失效
    带反馈回路的电子设备

    公开(公告)号：US5459483A

    公开(公告)日：1995-10-17

    申请号：US275055

    申请日：1994-07-13

    申请人： Martin J. Edwards

    发明人： Martin J. Edwards

    IPC分类号： G02F1/133 ,  G09G3/36 ,  G11C27/04 ,  H01L27/146 ,  H04N5/335 ,  H04N5/357 ,  H04N5/66

    CPC分类号： H04N5/357 ,  G09G3/3688 ,  G11C27/04

    摘要： Thin-film circuits comprising e.g. TFTs have inferior performance as compared with monolithic integrated circuits, and this inferior performance limits their use for e.g. drive circuits in large-area electronic devices such as an active matrix liquid-crystal display. In accordance with the invention, feedback with an external amplifier (150) is used to enhance the performance of a thin-film circuit. The feedback is taken from parallel nodes (40) of sequential stages (T1) of the circuit so that a common feedback line (51) and common external amplifier (150) can be used, thus reducing the number of substrate terminals and external connections required. Various buffers may be included between the feedback line (51) and the feedback terminal (56) to reduce the capacitive load on the line (51).

    摘要翻译： 薄膜电路包括例如 与单片集成电路相比，TFT具有较差的性能，并且这种较差的性能限制了它们在例如， 大面积电子器件中的驱动电路，例如有源矩阵液晶显示器。 根据本发明，使用外部放大器（150）的反馈来增强薄膜电路的性能。 反馈来自电路的顺序级（T1）的并行节点（40），使得可以使用公共反馈线（51）和公共外部放大器（150），从而减少衬底端子的数量和所需的外部连接 。 在反馈线（51）和反馈端（56）之间可以包括各种缓冲器，以减小线路（51）上的电容性负载。