公开(公告)号：US20240355883A1

公开(公告)日：2024-10-24

申请号：US18385537

申请日：2023-10-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyumin YOO ,  Myung Gil KANG ,  Dongwon KIM ,  Jongsu KIM ,  Beomjin PARK ,  Byeonghee SON

IPC分类号： H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0653

摘要： A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

公开(公告)号：US20240355879A1

公开(公告)日：2024-10-24

申请号：US18475322

申请日：2023-09-27

申请人： Samsung Electronics Co., Ltd.

发明人： SEUNG MIN SONG ,  JAEHONG LEE ,  KANG-ILL SEO

IPC分类号： H01L29/06 ,  H01L25/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L25/117 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising a pair of upper source/drain regions spaced apart from each other in a first horizontal direction and an upper gate electrode between the pair of upper source/drain regions; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower gate electrode; an upper insulating layer on the lower transistor structure, wherein the upper gate electrode is in the upper insulating layer; and a lower gate contact extending through the upper insulating layer and contacting the lower gate electrode, a center of the upper gate electrode in a second horizontal direction and a center of the lower gate electrode in the second horizontal direction are offset from each other in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

公开(公告)号：US12127435B2

公开(公告)日：2024-10-22

申请号：US18140530

申请日：2023-04-27

申请人： Samsung Display Co., Ltd.

发明人： Jae Bum Han ,  Moon Sung Kim ,  Young Gil Park ,  Soo Im Jeong

IPC分类号： H01L29/08 ,  H10K59/121 ,  H10K59/40 ,  G09G3/3233 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12

CPC分类号： H10K59/1213 ,  H10K59/40 ,  G09G3/3233 ,  G09G2300/0426 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/66757 ,  H01L29/78675 ,  H10K59/1201

摘要： A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

公开(公告)号：US12125922B2

公开(公告)日：2024-10-22

申请号：US18357491

申请日：2023-07-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sai-Hooi Yeong ,  Bo-Feng Young ,  Chien Ning Yao ,  Chi On Chui

IPC分类号： H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

公开(公告)号：US12125906B2

公开(公告)日：2024-10-22

申请号：US17563141

申请日：2021-12-28

申请人： DENSO CORPORATION

发明人： Shinichiro Yanagi ,  Yusuke Nonaka ,  Syogo Ikeura

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/7824 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/404

摘要： In a semiconductor device having a lateral transistor, a source wiring layer is disposed above at least a part of an interlayer insulating film. The interlayer insulating film is electrically connected to a source electrode and is extended toward a drain region to form a source field plate.

公开(公告)号：US12125894B2

公开(公告)日：2024-10-22

申请号：US18383926

申请日：2023-10-26

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics France

发明人： Alexis Gauthier ,  Pascal Chevalier

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L21/26513

摘要： A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US12125888B2

公开(公告)日：2024-10-22

申请号：US16642861

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/41725 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US12125848B2

公开(公告)日：2024-10-22

申请号：US18132924

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching Wang ,  Chun-Chung Su ,  Chung-Wei Wu ,  Jon-Hsu Ho ,  Kuan-Lun Cheng ,  Wen-Hsing Hsieh ,  Wen-Yuan Chen ,  Zhi-Qiang Wu

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US12125750B2

公开(公告)日：2024-10-22

申请号：US18118505

申请日：2023-03-07

申请人： Samsung Electronics Co., Ltd.

发明人： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/823462 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/6656

摘要： A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20240347639A1

公开(公告)日：2024-10-17

申请号：US18357172

申请日：2023-07-24

申请人： Wenzhou University

发明人： Hao Ye ,  Pengjun WANG ,  Xuejie Zhang ,  Yijian SHI ,  Gang LI ,  Bo CHEN ,  Zhening Shen

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L27/0924 ,  H01L29/086 ,  H01L29/0882 ,  H01L29/7827 ,  H01L29/78645 ,  H01L29/78696

摘要： Disclosed is a TFET with an OR-AND logic function. By arranging a horizontal channel and a vertical channel in different directions, three gates are not connected and will not be affected by each other, and can control the current of a whole channel jointly; when a first gate and a second gate are both at a high level, the TFET will be turned on, and when the first gate and a third gate are both at a high level, the TFET will also be turned on; the horizontal channel not only isolates the second gate from the third gate, but also reduces the strength of coupling between the second gate and the third gate, so only a small current passes through the horizontal channel when the second gate and the third gate are both at a high level, and the TFET will not be turned on at this moment.