公开(公告)号：US20150001990A1

公开(公告)日：2015-01-01

申请号：US14378267

申请日：2013-02-13

Applicant: Commissariat a l'energie atomique et aux ene alt ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Ollier ,  Stephane Monfray ,  Thomas Skotnicki ,  Ulrich Soupremanien

IPC: H02N2/18 ,  H01L41/08 ,  H01L41/047

CPC classification number: H02N2/185 ,  H01L41/047 ,  H01L41/08 ,  H02N2/18

Abstract: A device for converting heat energy into electrical energy including cells, the cells including: a first cavity with one wall for contacting a heat source; a second cavity with one wall for contacting a cold source; a primary channel between the first cavity and the second cavity transporting a fluid as liquid drops, the primary channel providing transport of liquid fluid drops from the second cavity to the first cavity; at least one secondary channel between the first cavity and the second cavity transporting the fluid as a gas; a piezoelectric material provided in one of the cavities; and a fluid as a liquid and gas contained within the cell.

Abstract translation: 一种用于将热能转换成包括电池的电能的装置，所述电池包括：具有用于接触热源的一个壁的第一腔; 具有用于接触冷源的一个壁的第二腔; 所述第一腔和所述第二腔之间的主要通道以液体的形式输送流体，所述主要通道提供液体流体液体从所述第二腔向所述第一腔的输送; 所述第一腔和所述第二腔之间的至少一个次通道作为气体输送所述流体; 设置在其中一个空腔中的压电材料; 以及作为包含在电池内的液体和气体的流体。

公开(公告)号：US20140361440A1

公开(公告)日：2014-12-11

申请号：US14287343

申请日：2014-05-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： PIERRE BAR ,  Simon GOUSSEAU ,  Yann BEILLIARD

IPC: H01L23/373 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.

Abstract translation: 用于在衬底内部生产至少一个穿硅的方法可包括在衬底的第一侧从衬底的第一侧形成空腔，直到导电部分出现。 该方法还可以包括在空腔的底部和壁上形成导电层，并且至少部分地在空腔外部的第一侧上形成导电层。 该方法还可以包括用至少一种相变材料至少部分地填充空腔。 另一方面涉及三维综合结构。

公开(公告)号：US08896121B2

公开(公告)日：2014-11-25

申请号：US13765760

申请日：2013-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/492 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/4924 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80097 ,  H01L2224/80357 ,  H01L2225/06513 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/05042 ,  H01L2924/04642 ,  H01L2924/059 ,  H01L2924/049

Abstract: An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.

Abstract translation: 半导体晶片/芯片的组件，其中两个晶片/芯片的相邻表面包括其中插入有相对的铜焊盘的绝缘层。 绝缘层由选自包括氮化硅和氮化碳的组的材料制成。

公开(公告)号：US20140292374A1

公开(公告)日：2014-10-02

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US20140284769A1

公开(公告)日：2014-09-25

申请号：US14220406

申请日：2014-03-20

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Aomar Halimaoui ,  Jean-Michel Hartmann

IPC: H01L21/02

CPC classification number: H01L21/02694 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1054

Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Abstract translation: 本公开涉及一种方法，涉及：通过在布置在衬底上的硅层上外延生长来形成应变硅锗层; 注入原子以使硅层和硅锗层的下部非晶化，而不使硅锗层的表面部分非晶化; 并进行退火，以至少部分地使硅锗层松弛并使硅锗层和硅层的下部重新结晶，使得硅层变成应变硅层。

公开(公告)号：US08828882B2

公开(公告)日：2014-09-09

申请号：US13713135

申请日：2012-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Françcois Leverd

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/76237 ,  H01L29/0649

Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.

Abstract translation: 通过在具有开口的衬底上沉积蚀刻掩模，通过开口蚀刻沟槽以及掺杂沟槽的壁，在半导体衬底中形成沟槽。 蚀刻步骤包括具有蚀刻功能的第一相，其蚀刻蚀刻掩模下的衬底，以及具有小于第一相的功率的蚀刻功率集的第二相。 此外，通过蚀刻掩模的开口施加沟槽的壁的掺杂。

公开(公告)号：US20140217520A1

公开(公告)日：2014-08-07

申请号：US14169913

申请日：2014-01-31

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat à I'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract translation: 一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度 下部，并且在其上部比第一长度短的第二长度。

公开(公告)号：US20140210071A1

公开(公告)日：2014-07-31

申请号：US14155007

申请日：2014-01-14

Applicant: Anne Lombardot ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US20140070158A1

公开(公告)日：2014-03-13

申请号：US14018223

申请日：2013-09-04

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Francois Nodin ,  Veronique Sousa ,  Sandrine Lhostis

IPC: H01L45/00

CPC classification number: H01L45/1246 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/165 ,  H01L45/1683

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.

Abstract translation: 一种存储单元，包括由布置在下电极和上电极之间的相变材料制成的通孔，其中所述通孔包括横向围绕周边区域的中心区域，所述中心区域的结晶和熔融温度分别低于 那些周边地区。

公开(公告)号：US20130286540A1

公开(公告)日：2013-10-31

申请号：US13803619

申请日：2013-03-14

Applicant: NXP B.V. (Dutch Corporation) ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Farcy ,  Maryline Thomas ,  Joaquin Torres ,  Sonarith Chhun ,  Laurent-Georges Gosset

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G4/008 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.

Abstract translation: 一种形成金属 - 绝缘体 - 金属电容器的方法，其具有由电介质层隔开的顶板和底板，所述顶板和底板中的一个具有延伸到顶板和底板中的另一个中的相应空腔中的至少一个突起， 方法包括在基底表面上生长一个或多个纳米纤维的步骤。