公开(公告)号：US07525160B2

公开(公告)日：2009-04-28

申请号：US11320309

申请日：2005-12-27

Applicant: Jack T. Kavalieros ,  Justin K. Brask ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Jack T. Kavalieros ,  Justin K. Brask ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.

Abstract translation: 本发明的实施例提供具有多个门的装置。 器件金属门的凹槽内的应力材料可能在器件的沟道区域中引起应力，从而提高器件的性能。

公开(公告)号：US20090085027A1

公开(公告)日：2009-04-02

申请号：US11864963

申请日：2007-09-29

Applicant: Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

Inventor： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

IPC: H01L29/12 ,  H01L21/205

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/7851

Abstract: The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20090057648A1

公开(公告)日：2009-03-05

申请号：US11847780

申请日：2007-08-30

Applicant: Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

Inventor： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

IPC: H01L29/205 ,  H01L21/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/267 ,  H01L29/66431

Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US07485503B2

公开(公告)日：2009-02-03

申请号：US11292399

申请日：2005-11-30

Applicant: Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/335 ,  H01L21/338 ,  H01L27/108

CPC classification number: H01L21/314 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7784

Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract translation: 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。

公开(公告)号：US20080237719A1

公开(公告)日：2008-10-02

申请号：US11729198

申请日：2007-03-28

Applicant: Brian S. Doyle ,  Suman Datta ,  Jack T. Kavalieros ,  Rafael Rios

Inventor： Brian S. Doyle ,  Suman Datta ,  Jack T. Kavalieros ,  Rafael Rios

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A multi-gate structure includes a substrate (110, 210, 410), an electrically insulating layer (120, 220, 420) over the substrate, and a first semiconducting fin (130, 230, 430) above the electrically insulating layer. The first semiconducting fin includes a top region (131, 231, 431), a first side region (132, 232, 432), and a second side region (133, 233, 433). The top region, the first side region, and the second side region have doping concentrations that are substantially equal to each other. The multi-gate structure may be made by depositing a solid source material (510) over the semiconducting fin, and by annealing the multi-gate structure such that dopants from the solid source material diffuse into the semiconducting fin and uniformly dope the top region and the first and second side regions.

Abstract translation: 多栅极结构包括衬底（110,210,410），在衬底上方的电绝缘层（120,220,420）以及在电绝缘层上方的第一半导电翅片（130,230,430）。 第一半导体鳍片包括顶部区域（131,231,431），第一侧面区域（132,232,432）和第二侧面区域（133,233,433）。 顶部区域，第一侧面区域和第二侧面区域具有彼此基本相等的掺杂浓度。 多栅极结构可以通过在半导体鳍上沉积固体源材料（510）并且通过退火多栅极结构使得来自固体源材料的掺杂剂扩散到半导体翅片中并且均匀地掺杂顶部区域和 第一和第二侧区域。

公开(公告)号：US20080237577A1

公开(公告)日：2008-10-02

申请号：US11728891

申请日：2007-03-27

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L21/84

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US20070284613A1

公开(公告)日：2007-12-13

申请号：US11450744

申请日：2006-06-09

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L31/00 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

Abstract translation: 描述了形成包含三种或更多种电荷 - 中性晶格形成原子的应变诱导半导体区域的方法。 在一个实施方案中，形成包含三个或更多种电荷 - 中性晶格形成原子的应变诱导半导体区域，横向邻近晶体衬底导致赋予晶体衬底的单轴应变。 因此，可以提供应变晶体衬底。 在另一个实施方案中，具有三种或更多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底施加应变，其中半导体区域的晶格常数不同于晶体衬底的晶格常数。

公开(公告)号：US07138316B2

公开(公告)日：2006-11-21

申请号：US10669064

申请日：2003-09-23

Applicant: Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

Abstract: A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

Abstract translation: 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US06667232B2

公开(公告)日：2003-12-23

申请号：US09208268

申请日：1998-12-08

Applicant: Steven J. Keating ,  Robert S. Chau ,  Reza Arghavani ,  Jack T. Kavalieros ,  Douglas W. Barlage

Inventor： Steven J. Keating ,  Robert S. Chau ,  Reza Arghavani ,  Jack T. Kavalieros ,  Douglas W. Barlage

IPC: H01L214763

CPC classification number: H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3143 ,  H01L29/51 ,  H01L29/518 ,  H01L2924/0002 ,  Y10S438/954 ,  H01L2924/00

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

Abstract translation: 形成适合用作MOSFET中的栅介质层的电介质层的方法包括在低于大约80℃的温度下钝化半导体衬底的表面并使钝化层氮化。 在特定实施例中，钝化硅晶片包括在约24℃下形成羟基硅酸盐层。在本发明的另一方面，集成电路包括多个绝缘栅场效应晶体管，其中多个 晶体管具有氮化钝化层的栅介质层。

公开(公告)号：US20230197804A1

公开(公告)日：2023-06-22

申请号：US17556627

申请日：2021-12-20

Applicant: Nazila HARATIPOUR ,  Gilbert DEWEY ,  I-Cheng TUNG ,  Nancy ZELICK ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS

Inventor： Nazila HARATIPOUR ,  Gilbert DEWEY ,  I-Cheng TUNG ,  Nancy ZELICK ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS

IPC: H01L29/417 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L29/45

Abstract: Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is adjacent to the gate structure. A conductive trench contact structure is on the epitaxial source or drain structure. The conductive trench contact structure includes a first planar layer on the epitaxial source or drain structure, a second planar layer on the first planar layer, and a conductive fill material on the second planar layer.