Abstract:
Antenna array calibration for wireless charging is disclosed. In one aspect, an initial calibration sequence is performed each time a wireless charging station is powered on. The initial calibration sequence utilizes a reference antenna element, which is an antenna element randomly selected from a plurality of antenna elements in the wireless charging station, to determine relative receiver phase errors between the reference antenna element and each of the other antenna elements in an antenna array. In another aspect, a training sequence is performed after completing the initial calibration sequence to determine total relative phase errors between the reference antenna element and each of the other antenna elements in the antenna array. Adjustments can then be made to match respective total relative phase errors among the plurality of antenna elements to achieve phase coherency among the plurality of antenna elements for improved wireless charging power efficiency.
Abstract:
This disclosure relates generally to directional couplers. In one embodiment, a directional coupler includes a first port, a second port, a third port, a first inductive element, a second inductive element, a first switchable path, and a second switchable path. The first inductive element is coupled between the first port and the second port, while the second inductive element is mutually coupled to the first inductive element. The first switchable path is configured to be opened and closed, wherein the first switchable path is coupled between a first location of the second inductive element and the third port. The second switchable path is configured to be opened and closed, wherein the second switchable path is coupled between a second location of the second inductive element and the third port. In this manner, a directivity of the directional coupler can be switched between a forward direction and a reverse direction.
Abstract:
Envelope power supply circuitry includes an envelope power converter circuitry and envelope tracking circuitry. The envelope power converter circuitry receives an envelope power converter control signal from the envelope tracking circuitry and a supply voltage and provides an envelope power supply signal for an amplifier based thereon. In a first mode of operation, the envelope power converter control signal is provided such that the envelope power supply signal causes the gain of the amplifier to remain substantially constant over a range of input power provided to the amplifier. In a second mode of operation, the envelope power converter control signal is provided such that the envelope power supply signal remains substantially constant for values within the range of input power below a predetermined threshold, and such that the envelope power supply signal causes the gain of the amplifier to remain substantially constant for other values.
Abstract:
A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current.
Abstract:
A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.
Abstract:
Aspects disclosed in the detailed description include a wireless charging circuit comprising a radio frequency (RF) power harvesting circuit. In one aspect, the RF power harvesting circuit is configured to harvest a wireless RF charging signal provided by a wireless charging station to generate a direct-current (DC) charging signal to charge a battery, for example, a lithium-ion (Li-ion) battery, in a battery-operated electronic device. In another aspect, a wireless charging controller controls the RF power harvesting circuit to dynamically increase or decrease an effective charging power of the DC charging signal according to a target charging power determined according to a charging profile of the battery. By dynamically adjusting the effective charging power provided to the battery according to the charging profile of the battery, it is possible to provide fast charging to the battery while protecting the battery from overcharging damage.
Abstract:
Analog-to-digital pulse width modulation circuitry includes thermometer code generator circuitry, clock generator circuitry, delay selection circuitry, and an output stage. The thermometer code generator circuitry is adapted to generate a digital thermometer code based upon a received analog input voltage. The clock generator circuitry is adapted to generate a reference clock and a plurality of delayed clock signals. The delay selection circuitry is connected between the thermometer code generator circuitry and the clock generator circuitry, and is adapted to select one of the delayed clock signals to present to the output stage based upon the generated thermometer code. The selected delayed clock signal is delayed by an amount of time that is proportional to the generated thermometer code. The reference clock signal and the selected delayed clock signal are delivered to the output stage where they are used to generate a pulse width modulated output signal.
Abstract:
The disclosure describes a dual hybrid duplexer including two hybrid couplers, two intra-filters, a tunable isolation load, and a phase shifter. The phase shifter may be located at the isolation port. The phase shifter may be located at the antenna port. In one embodiment, a dual hybrid duplexer includes two hybrid couplers, two intra-filters, a tunable isolation load, a first phase shifter located at the isolation port, and a second phase shifter located at the antenna port. The first and second phase shifters have a difference of 90 degrees (plus or minus 10 degrees).
Abstract:
In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.
Abstract:
A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.