公开(公告)号：US09275748B2

公开(公告)日：2016-03-01

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20150255165A1

公开(公告)日：2015-09-10

申请号：US14196839

申请日：2014-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/0425 ,  G11C2216/04

Abstract: Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于低功率纳米闪速存储器件的改进的感测电路。

公开(公告)号：US09123822B2

公开(公告)日：2015-09-01

申请号：US13958483

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

公开(公告)号：US09123431B2

公开(公告)日：2015-09-01

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

公开(公告)号：US09123401B2

公开(公告)日：2015-09-01

申请号：US13652447

申请日：2012-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C8/08

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

Abstract translation: 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

公开(公告)号：US20150206788A1

公开(公告)日：2015-07-23

申请号：US14162309

申请日：2014-01-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Wang ,  Chien-Sheng Su

IPC: H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

公开(公告)号：US20150200278A1

公开(公告)日：2015-07-16

申请号：US14665079

申请日：2015-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Mandana Tadayoni ,  Nhan Do

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract translation: 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

公开(公告)号：US20140269062A1

公开(公告)日：2014-09-18

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20140269061A1

公开(公告)日：2014-09-18

申请号：US13958415

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  H01L27/11519

Abstract: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于高级纳米闪存器件的改进的感测电路和改进的位线布局。

公开(公告)号：US20140269058A1

公开(公告)日：2014-09-18

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/34 ,  G11C16/12

CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。