公开(公告)号：US12154893B2

公开(公告)日：2024-11-26

申请号：US17806895

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/00 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.

公开(公告)号：US12112792B2

公开(公告)日：2024-10-08

申请号：US17712935

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0656 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/08 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/78 ,  H01L22/12 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  G06F2213/28 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/1601 ,  H01L2224/16221 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1436

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

公开(公告)号：US12107050B2

公开(公告)日：2024-10-01

申请号：US17325090

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L27/0688 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.

公开(公告)号：US20240282620A1

公开(公告)日：2024-08-22

申请号：US18649986

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L29/66568 ,  H01L29/78 ,  H10B12/485 ,  H01L27/0694 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H10B12/09

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US12058853B2

公开(公告)日：2024-08-06

申请号：US17115469

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Surendranath C. Eruvuru

IPC: H10B41/27 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/823437 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/092 ,  H10B43/27

Abstract: An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US12046582B2

公开(公告)日：2024-07-23

申请号：US18051459

申请日：2022-10-31

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L28/60 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

公开(公告)号：US20240194287A1

公开(公告)日：2024-06-13

申请号：US18525403

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C29/025

Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.

公开(公告)号：US20240136295A1

公开(公告)日：2024-04-25

申请号：US18400745

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L27/0688 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US20240072004A1

公开(公告)日：2024-02-29

申请号：US18237259

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L28/60 ,  H01L25/18 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first layer of dielectric material at which a first portion of conductive material implementing a first portion of a passive circuit component is at least partially disposed. The second semiconductor die includes a second layer of dielectric material at which a second portion of conductive material implementing a second portion of the passive circuit component is at least partially disposed. A first contact pad at the first layer of dielectric material and a second contact pad at a second layer of dielectric material are coupled to create an interconnect electrically coupling the first semiconductor die and the second semiconductor die. A metal-metal bond is formed between the first portion of the passive circuit component and the second portion of the passive circuit component to create the passive circuit component.

公开(公告)号：US20240063094A1

公开(公告)日：2024-02-22

申请号：US17892034

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/13 ,  H01L21/76898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/73204 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L21/308

Abstract: A semiconductor device includes a semiconductor substrate including a cavity and a peripheral region surrounding the cavity. The peripheral region includes a first surface and a second surface opposite the first surface. The cavity extends from the first surface partially through the semiconductor substrate to a third surface. The third surface is parallel to the first surface and is located between the first surface and the second surface. The semiconductor device also includes a plurality of through-silicon vias (TSVs) extending between the first surface and the third surface.