公开(公告)号：US07532242B1

公开(公告)日：2009-05-12

申请号：US10899540

申请日：2004-07-26

Applicant: Bryan J. Chen

Inventor： Bryan J. Chen

IPC: H04N5/335

CPC classification number: H04N5/3743 ,  G11C19/00 ,  G11C27/02 ,  H01L27/144 ,  H04N5/341 ,  H04N5/37206 ,  H04N5/378

Abstract: A series of time delay integration TDI stages each integrate a photocurrent from a separate detector such as detectors in an array. In a first stage 20, a first integrator is initialized with a fixed bias 30, and integrates a signal from a first detector 22 during a first time interval. Next, a reset switch 26n causes that integrated first detector signal to bias a second integrator 24n. During a second integration interval, the second integrator integrates a signal from a second detector 22n. Multiple stages may be arranged in series so that an integrated signal from a previous stage biases an integrator in the current stage. At a final stage, an Nth integrator outputs the resulting signal Vfinal. Any bias used to initialize the first integrator is removed from Vfinal to achieve a total integrated signal from the detectors. A bi-directional switch 38 at each stage enables a forward or backward scan of the detectors.

Abstract translation: 一系列时间延迟积分TDI级每个集成来自单独检测器的光电流，例如阵列中的检测器。 在第一级20中，以固定偏置30初始化第一积分器，并且在第一时间间隔期间对来自第一检测器22的信号进行积分。 接下来，复位开关26n使得积分的第一检测器信号偏置第二积分器24n。 在第二积分间隔期间，第二积分器积分来自第二检测器22n的信号。 可以串联布置多个级，使得来自先前级的积分信号在当前阶段偏置积分器。 在最后阶段，第N个积分器输出结果信号Vfinal。 用于初始化第一个积分器的任何偏压从Vfinal中去除，以实现来自检测器的总的积分信号。 在每个阶段的双向开关38能够进行检测器的向前或向后扫描。

公开(公告)号：US07309854B2

公开(公告)日：2007-12-18

申请号：US11246117

申请日：2005-10-11

Applicant: Torsten Wipiejewski

Inventor： Torsten Wipiejewski

IPC: H01L31/00

CPC classification number: H01L31/1085 ,  H01L27/144 ,  H01L31/02024

Abstract: An opto-electronic device comprising a plurality of photo-detectors, each said photo-detector comprises a plurality of optical detection segments which are connected in parallel, the optical detection segments of said plurality of optical-detectors are interposed so that an optical detection segment of a photo-detector is intermediate optical detection segments of another photo-detector and an optical detection segment of that another photo-detector is intermediate optical detection segments of said photo-detector.

公开(公告)号：US20070164393A1

公开(公告)日：2007-07-19

申请号：US10596035

申请日：2004-12-06

Applicant: Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

Inventor： Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

IPC: H01L29/00

CPC classification number: H01L27/144 ,  H01L31/02016 ,  H01L31/022408 ,  H01L31/10

Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evalation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

Abstract translation: 本发明的目的是配置光电检测器（10），使得在现有技术中已知的检测器上特别是当对评估电子器件进行单片整合时，不会产生用于处理低发光强度的缺点。 所述目的通过用于处理低发光强度的光电检测器实现，其包括单片集成跨阻抗放大器和单片集成评估电子器件。 实际的光电池组件（20）被分配给光优选落在其上的芯片面。 电子电路部件（30）布置在相对的芯片面上。 在光电管和电子电路之间的电连接（40）在垂直于芯片法线的方向上具有延伸。

公开(公告)号：US20070164281A1

公开(公告)日：2007-07-19

申请号：US11335042

申请日：2006-01-18

Applicant: Po-Sheng Shih

Inventor： Po-Sheng Shih

IPC: H01L29/04

CPC classification number: H01L29/78633 ,  H01L27/12 ,  H01L27/144 ,  H01L29/78609 ,  H01L31/147

Abstract: An input display is provided in the present invention. The input display includes a thin film transistor (TFT) and a light blocking layer. The TFT includes a low-field electrode, a high-field electrode connected to the low-field electrode with a connecting section, and a field-effect area positioned on the connecting section and connected to the high-field electrode, wherein a PN junction field is formed in the field-effect area when the TFT is switched off. The light blocking layer corresponds to the high-field electrode and hides the field-effect area from all incident light from the TFT.

Abstract translation: 在本发明中提供输入显示。 输入显示器包括薄膜晶体管（TFT）和遮光层。 TFT包括低场电极，连接到具有连接部分的低场电极的高场电极和位于连接部分上并连接到高场电极的场效应区域，其中PN结 当TFT关闭时，在场效应区域中形成场。 遮光层对应于高场电极，并隐藏来自TFT的所有入射光的场效应区域。

公开(公告)号：US20070105274A1

公开(公告)日：2007-05-10

申请号：US11591333

申请日：2006-11-01

Applicant: Eugene Fitzgerald

Inventor： Eugene Fitzgerald

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L27/14601 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/76254 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/144 ,  H01L27/1446 ,  H01L27/14683 ,  H01L27/15 ,  H01L27/156 ,  H01L31/0328 ,  H01L31/143 ,  H01L31/162 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.

Abstract translation: 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中，半导体结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 半导体结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层，设置在第一区域中的绝缘层上的单晶硅层和设置在第一单晶的至少一部分上的第二单晶半导体层 半导体层在第二区域中并且不存在于第一区域中。 第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。

公开(公告)号：US20070080285A1

公开(公告)日：2007-04-12

申请号：US11517928

申请日：2006-09-08

Applicant: Dov Lavi

Inventor： Dov Lavi

IPC: H01L31/00

CPC classification number: H01L31/02024 ,  H01L27/144 ,  H01L31/02161 ,  H01L31/0232

Abstract: The invention relates to a four-quadrant detector based optical system for detecting and tracking an optical spot, which comprises: (a) a four quadrant detector, which comprises four surfaces that are sensitive to light, said surfaces being separated one from the others by a dead zone surface which is non-sensitive to light radiation; (b) optics between said detector and the scenery, for acquiring an image of a light spot at the scenery, and for impinging the image of the same on said surfaces of the decoder; and (c) a refraction element between said detector and the other optics, which comprises grooves for diverting only the light rays coming from the scenery and directed toward the dead zone, each to a corresponding proximate sensitive to light surfaces of the decoder, while not disturbing the other coming light rays, wherein said refraction element has no physical contact with any of said detector surfaces.

Abstract translation: 本发明涉及一种用于检测和跟踪光点的四象限检测器的光学系统，其包括：（a）四象限检测器，其包括对光敏感的四个表面，所述表面通过 对光辐射不敏感的死区表面; （b）所述检测器和风景之间的光学元件，用于获取风景中的光点的图像，并将其图像投影到解码器的所述表面上; 和（c）所述检测器和其它光学器件之间的折射元件，其包括用于仅将来自风景的光线转向死区的凹槽，每个至少对应于解码器的光表面的相应接近，而不 扰乱另外的光线，其中所述折射元件与任何所述检测器表面没有物理接触。

公开(公告)号：US20070080284A1

公开(公告)日：2007-04-12

申请号：US11246117

申请日：2005-10-11

Applicant: Torsten Wipiejewski

Inventor： Torsten Wipiejewski

IPC: H01L31/00

CPC classification number: H01L31/1085 ,  H01L27/144 ,  H01L31/02024

Abstract: An opto-electronic device comprising a plurality of photo-detectors, each said photo-detector comprises a plurality of optical detection segments which are connected in parallel, the optical detection segments of said plurality of optical-detectors are interposed so that an optical detection segment of a photo-detector is intermediate optical detection segments of another photo-detector and an optical detection segment of that another photo-detector is intermediate optical detection segments of said photo-detector.

Abstract translation: 一种包括多个光检测器的光电器件，每个所述光检测器包括并联连接的多个光检测段，所述多个光检测器的光检测段被插入，使得光检测段 光检测器的中间光检测段是另一光检测器的中间光检测段，另一光检测器的光检测段是所述光检测器的中间光检测段。

公开(公告)号：US07157747B2

公开(公告)日：2007-01-02

申请号：US10731087

申请日：2003-12-10

Applicant: Mitsuru Mariyama ,  Masaru Kubo

Inventor： Mitsuru Mariyama ,  Masaru Kubo

IPC: H01L31/111

CPC classification number: H01L31/1113 ,  H01L27/144

Abstract: A channel isolation region 42 is formed over the entire width of an N-type silicon substrate 41, and photothyristors, in each of which an anode diffusion region 43, a P-gate diffusion region 44, a cathode diffusion region 45 are formed parallel to the channel isolation region 42 over almost the entire width of the N-type silicon substrate 41, are formed in a left-hand portion 40a and in a right-hand portion 40b and are wired inversely parallel. Thus, the inter-channel movement of residual holes during commutation is restrained by the channel isolation region 42, by which commutation failure is suppressed to improve a commutation characteristic. Further, an operating current large enough for controlling a load current of approx. 0.2 A is obtained although a chip is divided by the channel isolation region 42. Therefore, using this bidirectional photothyristor chip makes it possible to implement an inexpensive SSR with a main thyristor eliminated.

Abstract translation: 沟道隔离区域42形成在N型硅衬底41的整个宽度上，并且其中阳极扩散区域43，P栅极扩散区域44，阴极扩散区域45平行于其形成的光电晶体管 在N型硅衬底41的几乎整个宽度上的沟道隔离区域42形成在左手部分40a和右手部分40b中，并且被反向并联。 因此，换向期间的剩余空穴的通道间移动被通道隔离区域42抑制，通过该通道隔离区域42抑制了换向失败，从而改善换流特性。 此外，工作电流足够大以控制大约的负载电流。 即使芯片被通道隔离区域42分割，也可以获得0.2A。 因此，通过使用这种双向光电晶体管芯片，可以实现廉价的SSR，其中省略了主晶闸管。

公开(公告)号：US07148481B2

公开(公告)日：2006-12-12

申请号：US10982335

申请日：2004-11-05

Applicant: Michel Vilain

Inventor： Michel Vilain

IPC: G01J5/00

CPC classification number: H01L27/144 ,  G01J5/20 ,  H01L27/146

Abstract: An infrared detection device including a matrix of bolometric detectors electrically connected to a reading circuit. Each of the detectors includes at least two electrically conductive thermal insulation structures insulated from one another and fitted in contact at one of their ends with an active zone consisting of a bolometric material. One of the structures is electrically connected at its other end to the reading circuit by a cold electrical connection that is kept at a substantially constant potential. The other structure is electrically connected at its other end to the reading circuit by a hot electrical connection, which is connected in series with a switch integrated into the reading circuit. At least two adjacent bolometric detectors are connected by a common electrical connection to the substantially constant potential of the reading circuit.

Abstract translation: 一种红外线检测装置，包括电连接到读取电路的测温检测器矩阵。 每个检测器包括彼此绝缘并且在其一个端部处接触的至少两个导电保温结构和由热应变材料组成的活动区域。 其中一个结构通过保持在基本上恒定电位的冷电连接而在另一端电连接到读取电路。 另一个结构在其另一端通过热电连接而与读取电路电连接，该热电连接与集成到读取电路中的开关串联连接。 至少两个相邻的测辐射检测器通过公共电连接连接到读取电路的基本上恒定的电位。

公开(公告)号：US07109051B2

公开(公告)日：2006-09-19

申请号：US10989940

申请日：2004-11-15

Applicant: Nigel G. Cave ,  Omar Zia

Inventor： Nigel G. Cave ,  Omar Zia

IPC: H01L21/00 ,  H01L21/338

CPC classification number: H01L27/144 ,  H01L27/15

Abstract: A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.