公开(公告)号：US09031378B2

公开(公告)日：2015-05-12

申请号：US13706620

申请日：2012-12-06

Applicant: VIA Technologies, Inc.

Inventor： Hsin-Hung Lin

IPC: H04N5/65 ,  H04N5/765 ,  H04N5/783 ,  H04N21/41 ,  H04N21/4143 ,  H04N21/432 ,  H04N21/436 ,  H04N21/4363

CPC classification number: H04N5/765 ,  H04N5/783 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4325 ,  H04N21/43622 ,  H04N21/43637

Abstract: A method and a playback control device are provided. The method, performed by the playback control device, includes: receiving a first request to playback a first data of a first wireless multimedia data type having a first priority; and playing back the first data if no other data of a wireless multimedia data type having a priority higher than the first priority is received.

Abstract translation: 提供了一种方法和播放控制装置。 由播放控制装置执行的方法包括：接收第一请求以回放具有第一优先级的第一无线多媒体数据类型的第一数据; 以及如果没有接收到具有高于第一优先级的优先级的无线多媒体数据类型的其他数据，则回放第一数据。

公开(公告)号：US20150089088A1

公开(公告)日：2015-03-26

申请号：US14452784

申请日：2014-08-06

Applicant: Via Technologies, Inc.

Inventor： Chia-Ying KUO ,  Yi-Lin LAI

IPC: G06F13/14 ,  G06F3/06

CPC classification number: G06F13/4086 ,  G06F13/20

Abstract: An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.

Abstract translation: 公开了一种将外部电子设备的主体连接到主机的接口控制器，以及使用接口控制器的电子设备和外部电子控制器的控制方法。 接口控制器具有控制单元和非易失性存储器。 控制单元被配置为当从主体检索到的链接信息已被写入非易失性存储器时，向终端发送终止信号。 当主机响应于终止信号发出链接信息请求时，控制单元使用存储在非易失性存储器中的链接信息来响应链接信息请求。

公开(公告)号：US20150081960A1

公开(公告)日：2015-03-19

申请号：US14548549

申请日：2014-11-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Liang CHEN ,  Chen XIU

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

Abstract translation: 本发明提供一种存储装置。 存储器件包括闪存，存储器和控制器。 闪存包括用于数据存储的多个块。 存储器存储记录其中的块的逻辑地址和物理地址之间的关系的地址映射表。 控制器将存储在存储器中的地址映射表分成多个映射表单元，更新存储在映射表单元中的逻辑地址和物理地址之间的关系，确定对闪速存储器执行的数据访问是否满足条件 特定要求，并且当数据访问满足特定要求的条件时，控制器从映射表单元中选择目标映射表单元，并将目标映射表单元和对应的时间戳作为映射表单元数据存储到 闪存

公开(公告)号：US08982655B1

公开(公告)日：2015-03-17

申请号：US13972794

申请日：2013-08-21

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/16 ,  G06F11/1008 ,  G11C29/802

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract translation: 可以预期用于存储和提供配置数据给微处理器的装置。 该设备具有设置在管芯上的核心和熔丝阵列，该熔丝阵列设置在管芯上并且耦合到核心，其中熔丝阵列包括用于核心的压缩配置数据编程的多个半导体熔丝，其中压缩的配置数据 通过对与核心对应的虚拟熔丝阵列内的数据进行压缩而产生，并且其中核心在上电/复位时对压缩的配置数据进行访问和解压缩，以用于初始化核心内的元件。

公开(公告)号：US20150067666A1

公开(公告)日：2015-03-05

申请号：US14281786

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/445

CPC classification number: G06F8/665 ,  G06F8/654 ,  G06F8/656 ,  G06F8/67 ,  G06F9/268 ,  G06F9/328 ,  G06F11/366 ,  Y02B60/183 ,  Y02D10/42

Abstract: A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.

Abstract translation: 微处理器包括多个处理核心，其中多个处理核心中的每一个执行微代码并且包括用于修补微代码的硬件。 多个处理核心的第一核心被配置为遇到指示第一核心应用微代码补丁的指令。 多个处理核心的第一核心还被配置为响应于遇到该指令，通知微代码补丁的多个处理核心中的另一个的每个核心，并将微代码补丁应用于第一核心的硬件。 多个第一核心以外的多个处理核心的每个核心被配置为响应于第一核心被通知而将微码补丁应用于核心的硬件。

公开(公告)号：US20150067368A1

公开(公告)日：2015-03-05

申请号：US14281488

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F1/12 ,  G06F1/32 ,  G06F1/04

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract translation: 微处理器包括多个半导体管芯，耦合多个半导体管芯的总线以及多个处理核心。 处理核心的不同子集位于每个半导体管芯上。 每个管芯包括控制单元，该控制单元被配置为选择性地将相应的时钟信号控制到芯片的核心子集中的每一个。 对于子集的每个核心，响应于核心向控制单元写入值，控制单元被配置为关闭相应的时钟信号到核心，并将总线上的值写入到另一个的控制单元 死。 集中地，所有控制单元被配置为在时钟信号已经关闭到所有处理核之后同时打开到所有处理核的时钟信号。

公开(公告)号：US20150067219A1

公开(公告)日：2015-03-05

申请号：US14281729

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/38 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract translation: 微处理器包括指示器和多个处理核心。 多个处理核心中的每一个被配置为对指示器进行采样。 当指示符指示第一预定值时，多个处理核心被配置为将多个处理核心中的默认处理核心共同指定为自举处理器。 当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为将默认处理核以外的多个处理核中的一个统一指定为引导处理器。

公开(公告)号：US20150061119A1

公开(公告)日：2015-03-05

申请号：US14054850

申请日：2013-10-16

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/12 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract translation: 电路基板包括电路堆叠，图案化导电层，电介质层和多个增厚导电层。 电路堆叠有一个表面。 图案化的导电层位于电路堆叠的表面上并且具有多个迹线。 每条迹线都有一个粘结段。 电介质层位于电路堆叠的表面上并覆盖图案化的导电层。 此外，电介质层具有多个接合开口。每个接合开口暴露相应的接合段。 每个增稠导电层位于相应的粘结段上。 还提供了具有上述电路基板和制造电路基板的工艺的半导体封装结构。

公开(公告)号：US20150058598A1

公开(公告)日：2015-02-26

申请号：US13972609

申请日：2013-08-21

Applicant: VIA Technologies, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3885 ,  G06F9/5077 ,  G06F15/76 ,  G11C17/16

Abstract: An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

Abstract translation: 设想用于存储并向集成电路装置提供配置数据的装置，该装置具有熔丝阵列和多个芯。 保险丝阵列设置在管芯上。 熔丝阵列具有第一多个半导体熔丝和第二多个半导体熔丝。 多个芯设置在管芯上，其中多个芯中的每一个都耦合到熔丝阵列。 多个核心中的每一个包括阵列控制，被配置为访问第一和第二多个保险丝，并且被配置为根据第一和第二多个保险丝的内容来处理第一多个半导体熔丝的第一状态和第二多个半导体熔丝的第二状态 配置数据寄存器。

公开(公告)号：US20150055429A1

公开(公告)日：2015-02-26

申请号：US13972794

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F11/1008 ,  G11C29/802

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract translation: 可以预期用于存储和提供配置数据给微处理器的装置。 该设备具有设置在管芯上的核心和熔丝阵列，该熔丝阵列设置在管芯上并且耦合到核心，其中熔丝阵列包括用于核心的压缩配置数据编程的多个半导体熔丝，其中压缩的配置数据 通过对与核心对应的虚拟熔丝阵列内的数据进行压缩而产生，并且其中核心在上电/复位时对压缩的配置数据进行访问和解压缩，以用于初始化核心内的元件。