公开(公告)号：US20090048543A1

公开(公告)日：2009-02-19

申请号：US12222402

申请日：2008-08-08

申请人： Shan-Chi Ko

发明人： Shan-Chi Ko

IPC分类号： A61H1/00 ,  A61B5/00

CPC分类号： A61H39/02

摘要： The present invention discloses a method, system and module for determining the stimulated point of human body. The method includes defining the distributions of the plurality of collateral meridians of human and the plurality of body flow lines, thereby constructing the related information regarding the collateral meridians and the body flow lines based on the distributions of the plurality of collateral meridians and body flow lines, identifying the corresponding body flow lines based on the collateral meridians of the abnormal portions, determining one or a plurality of stimulated points based on the body flow fines and the corresponding information on abnormal positions, and applying the stimulations to the stimulated points for attenuating or recovering the abnormal portion. The system includes a process system to analyze the data inputted by the input/output module and data enclosed in the databases through the calculating module, and then the plurality of stimulated points can be obtained. Further, the module includes the distributions of the plurality of body flow lines and the stimulated points to determine one or a plurality of the stimulated points.

摘要翻译： 本发明公开了一种用于确定人体刺激点的方法，系统和模块。 该方法包括定义人体和多条身体流动线的多个副旁路经络的分布，从而基于多个旁路经线和身体流线的分布来构建关于旁路经线和身体流线的相关信息 基于所述异常部分的所述副旁路经络识别对应的身体流线，基于所述身体流动细节确定一个或多个受刺激点以及相应于异常位置的信息，以及将刺激应用于刺激点以进行衰减或 恢复异常部分。 该系统包括通过计算模块分析由输入/输出模块输入的数据和包含在数据库中的数据的处理系统，然后可以获得多个受激点。 此外，模块包括多个身体流动线和刺激点的分布以确定一个或多个刺激点。

公开(公告)号：US20080233765A1

公开(公告)日：2008-09-25

申请号：US11727133

申请日：2007-03-23

申请人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

发明人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

摘要翻译： 一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。 该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

公开(公告)号：US20080096380A1

公开(公告)日：2008-04-24

申请号：US11585610

申请日：2006-10-24

申请人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

摘要翻译： 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US07172964B2

公开(公告)日：2007-02-06

申请号：US10890622

申请日：2004-07-14

申请人： Chung Chi Ko ,  Syun Ming Jang

发明人： Chung Chi Ko ,  Syun Ming Jang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/0276 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/76831

摘要： A method comprises forming a low-dielectric constant (low-k) layer over a semiconductor substrate, forming an anti-reflective layer over the low-k layer, forming at least one opening in the anti-reflective layer and in the low-k layer, forming a nitrogen-free liner in the at least one opening, and forming at least one recess through the nitrogen-free liner, the anti-reflective layer, and at least partially into the low-k layer, the at least one recess is disposed over the at least one opening.

摘要翻译： 一种方法包括在半导体衬底上形成低介电常数（低k）层，在低k层上形成抗反射层，在抗反射层中形成至少一个开口，在低k 在所述至少一个开口中形成无氮衬里，以及通过所述无氮衬里，所述抗反射层形成至少一个凹部，并且至少部分地形成所述低k层，所述至少一个凹部 设置在至少一个开口上。

公开(公告)号：US20060063386A1

公开(公告)日：2006-03-23

申请号：US10949128

申请日：2004-09-23

申请人： Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

发明人： Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/302

CPC分类号： H01L21/02063 ,  G03F7/427 ,  Y10S438/958

摘要： A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.

摘要翻译： 等离子体处理操作使用N 2和H 2的气体混合物去除光致抗蚀剂膜并处理低k电介质材料。 等离子体处理操作通过在低k电介质材料上形成保护层来防止低k材料的劣化。 来自光致抗蚀剂层的碳被激活并与低k电介质复合，保持适当高的碳含量和合适的低介电常数。 等离子体处理操作使用构成气体混合物的至少10体积％的H 2 N 2气体混合物。

公开(公告)号：US20050227750A1

公开(公告)日：2005-10-13

申请号：US11056812

申请日：2005-02-10

申请人： Kevin Brase ,  Allen Michalik ,  Ethan Wood ,  Chi Ko ,  Derek Mann ,  Chris Park

发明人： Kevin Brase ,  Allen Michalik ,  Ethan Wood ,  Chi Ko ,  Derek Mann ,  Chris Park

IPC分类号： A63F1/00 ,  A63F9/24 ,  G07F17/32

CPC分类号： A63F1/00 ,  A63F9/24 ,  A63F2001/008 ,  A63F2009/2402 ,  A63F2009/2408 ,  A63F2009/2438 ,  G07F17/32 ,  G07F17/3209 ,  G07F17/3293

摘要： The present invention relates to an electronic game, including a housing, electronic circuitry positioned within the housing, and a display unit positioned within the housing and electrically coupled to the circuitry. A first sensor is electrically coupled to the circuitry and when activated initiates a first response from the circuitry. A second sensor electrically coupled to the circuitry and when activated prior to activating the first sensor initiates a second response from the circuitry.

摘要翻译： 电子游戏技术领域本发明涉及一种电子游戏，其包括壳体，位于壳体内的电子电路以及位于壳体内并电耦合到电路的显示单元。 第一传感器电耦合到电路，并且当激活时启动来自电路的第一响应。 电耦合到电路并且在激活第一传感器之前激活的第二传感器启动来自电路的第二响应。

公开(公告)号：US20050133931A1

公开(公告)日：2005-06-23

申请号：US11048073

申请日：2005-02-01

申请人： Syun-Ming Jang ,  Chung-Chi Ko ,  Tien-I Bao ,  Lih-Ping Li ,  Ai-Sen Liu

发明人： Syun-Ming Jang ,  Chung-Chi Ko ,  Tien-I Bao ,  Lih-Ping Li ,  Ai-Sen Liu

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.

公开(公告)号：US06806185B2

公开(公告)日：2004-10-19

申请号：US10246895

申请日：2002-09-19

申请人： Lain-Jong Li ,  Chung-Chi Ko

发明人： Lain-Jong Li ,  Chung-Chi Ko

IPC分类号： H01L214763

CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829

摘要： Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a patterned dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a patterned capping layer formed upon the patterned dielectric layer. The patterned capping layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 0 to about 200 degrees centigrade and a radio frequency power of from about 100 to about 1000 watts per square centimeter substrate area. The patterned capping layer provides for attenuated abrasive damage to the dielectric layer incident to the damascene method and is typically partially planarized incident to the damascene method.

摘要翻译： 在形成介于其图案之间的图案化导体层的镶嵌方法中，由相对低的介电常数介电材料法形成的图案化电介质层，采用形成在图案化电介质层上的图案化覆盖层。 图案化覆盖层使用等离子体增强化学气相沉积（PECVD）方法，依次使用有机硅烷碳和硅源材料，基底温度为约0至约200摄氏度，射频功率为约100至 约1000瓦/平方厘米衬底面积。 图案化盖层提供了对镶嵌方法入射的介电层的衰减的磨损损伤，并且通常部分地平坦化地入射到镶嵌法。

公开(公告)号：US08536064B2

公开(公告)日：2013-09-17

申请号：US12701927

申请日：2010-02-08

申请人： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

发明人： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

IPC分类号： H01L21/302

CPC分类号： H01L21/31105 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832

摘要： A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.

公开(公告)号：US08481412B2

公开(公告)日：2013-07-09

申请号：US12893399

申请日：2010-09-29

申请人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

发明人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

摘要翻译： 用于在衬底上形成互连的方法和装置包括在超低k电介质中的蚀刻图案，并且使用主动能量辅助烘烤从超低k电介质去除湿气。 在活性能量辅助烘烤期间，在约300至约400摄氏度的温度下，超低k电介质被加热并暴露于仅具有大于400nm波长的光约1至约20分钟。 活性能量辅助烘烤在湿清洗或化学机械抛光之后进行，或两者都进行。