公开(公告)号：US20070085205A1

公开(公告)日：2007-04-19

申请号：US11510066

申请日：2006-08-24

Applicant: Shang-Wei Chen ,  Zhao-Chong Zeng ,  Chung-Cheng Lien ,  Shih-Ping Hsu

Inventor： Shang-Wei Chen ,  Zhao-Chong Zeng ,  Chung-Cheng Lien ,  Shih-Ping Hsu

IPC: H01L21/44

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/82039 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device with electroless plating metal connecting layer and a method for fabricating the same are proposed. A supporting board with at least one cavity is provided. At least one semiconductor chip with a plurality of copper electrode pads is received in the cavity and an insulating protecting layer is formed on the semiconductor chip. A plurality of holes is formed in the insulating protecting layer to expose the copper electrode pads. An electroless plating metal connecting layer is formed on the copper electrode pads by electroless plating. Therefore, the electrically connecting process of the semiconductor chip is simplified and easily practiced, and the fabrication cost is reduced.

Abstract translation: 提出了一种具有化学镀金属连接层的半导体器件及其制造方法。 提供具有至少一个空腔的支撑板。 具有多个铜电极焊盘的至少一个半导体芯片被接收在空腔中，并且在半导体芯片上形成绝缘保护层。 在绝缘保护层中形成多个孔，露出铜电极焊盘。 通过化学镀在铜电极焊盘上形成化学镀金属连接层。 因此，简化并容易地实现了半导体芯片的电连接工艺，并降低了制造成本。

公开(公告)号：US20050239269A1

公开(公告)日：2005-10-27

申请号：US10947357

申请日：2004-09-23

Applicant: Chu-Chin Hu ,  Chung-Cheng Lien ,  Chi-Ming Chen ,  Sheng-Hsiang Yang ,  Meng-Da Chou

Inventor： Chu-Chin Hu ,  Chung-Cheng Lien ,  Chi-Ming Chen ,  Sheng-Hsiang Yang ,  Meng-Da Chou

IPC: H01L21/301 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L24/82 ,  H01L23/5389 ,  H01L24/19 ,  H01L29/0657 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082

Abstract: A method for releasing stress of an embedded chip and a chip embedded structure are proposed. Cutting processes are performed to a semiconductor chip before it is embedded in a circuit board to form cut-way portions at edges of the chip so as to allow stress to be released when the chip is subsequently embedded in the circuit board and a filler material is filled between the chip and the circuit board.

Abstract translation: 提出了一种释放嵌入式芯片和芯片嵌入式结构的应力的方法。 在将半导体芯片嵌入电路板中之前对半导体芯片进行切割处理，以在芯片的边缘处形成切割部分，以便当芯片随后嵌入电路板时允许释放应力，填充材料为 填充在芯片和电路板之间。

公开(公告)号：US08256106B2

公开(公告)日：2012-09-04

申请号：US12010345

申请日：2008-01-24

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

公开(公告)号：US07514770B2

公开(公告)日：2009-04-07

申请号：US11467310

申请日：2006-08-25

Applicant: Chia-Wei Chang ,  Chung-Cheng Lien

Inventor： Chia-Wei Chang ,  Chung-Cheng Lien

IPC: H01L23/02 ,  H05K3/30 ,  H05K1/16

CPC classification number: H01L23/5389 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10515 ,  Y10T29/4913 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack structure of a carrier board embedded with semiconductor components and a method for fabricating the same are proposed. The stack structure includes first and second carrier boards having a through hole respectively, first and second semiconductors component disposed in through holes of the first and second semiconductor components respectively, and a dielectric layer structure clamped between the first carrier board and the second carrier board and having a first dielectric layer formed on the first carrier board and an inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and an inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer.

Abstract translation: 提出了嵌入半导体部件的载体板的堆叠结构及其制造方法。 叠层结构包括分别具有通孔的第一和第二载体板，分别设置在第一和第二半导体部件的通孔中的第一和第二半导体部件以及夹在第一载体板和第二载体板之间的电介质层结构， 具有形成在所述第一载体板上的第一电介质层和所述第一半导体部件的非活性表面并填充在所述第一载体板和所述第一半导体部件之间的间隙中，形成在所述第二载体板上的第二介电层， 第二半导体部件，并且填充在第二载体板和第二半导体部件之间的间隙中，以及夹在第一介电层和第二介电层之间的接合层。

公开(公告)号：US07507915B2

公开(公告)日：2009-03-24

申请号：US11462604

申请日：2006-08-04

Applicant: Chia-Wei Chang ,  Lin-Yin Wong ,  Zao-Kuo Lai ,  Chung-Cheng Lien

Inventor： Chia-Wei Chang ,  Lin-Yin Wong ,  Zao-Kuo Lai ,  Chung-Cheng Lien

IPC: H05K1/16

CPC classification number: H05K1/185 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.

Abstract translation: 提出了嵌入半导体元件的载体板的堆叠结构及其制造方法。 提供了具有至少一个通孔的第一承载板和第二承载板。 第一保护层和第二保护层分别形成在第一和第二载体板的表面上。 至少一个第一半导体部件和至少一个第二半导体部件设置在第一和第二保护层上，分别容纳在第一和第二通孔中。 介电层层压在第一和第二载体板的表面之间，而不形成保护层。 因此，形成了具有减少的空间浪费的模块化封装结构。

公开(公告)号：US20090032930A1

公开(公告)日：2009-02-05

申请号：US11832466

申请日：2007-08-01

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Shang-Wei Chen ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Shang-Wei Chen ,  Kan-Jung Chia

IPC: H01L21/52 ,  H01L23/18

CPC classification number: H01L21/52 ,  H01L23/24 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.

Abstract translation: 具有嵌入其中的芯片的封装基板包括其中具有第一腔的第一铝基板; 第二铝基板，具有对应于第一空腔的第二腔; 设置在所述第一铝基板和所述第二铝基板之间的电介质层; 嵌入在所述第一腔和所述第二腔中的芯片，具有其上具有多个电极焊盘的活性表面; 以及设置在第一铝基板的表面和芯片的有源表面上的一个堆积结构，其中，所述积层结构具有电连接到电极焊盘的多个导电通孔。 通过使用铝或铝合金作为基材的材料，显着减少了基板翘曲。 另外，公开了一种制造具有嵌入其中的芯片的封装衬底的方法。

公开(公告)号：US20080185704A1

公开(公告)日：2008-08-07

申请号：US11701409

申请日：2007-02-02

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

IPC: H01L21/00 ,  H01L23/48

CPC classification number: H05K3/4608 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H05K1/053 ,  H05K1/183 ,  H05K3/445 ,  H05K3/4641 ,  H05K3/4697 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/0315

Abstract: A carrier plate structure having a chip embedded therein, comprises an aluminum plate having plural through-holes extending from the upper surface to the lower surface of the aluminum plate, a cavity therein, and an aluminum oxide layer formed on the surface of the aluminum plate; a chip embedded in the cavity with an active surface having plural electrode pads set thereon; and at least one build-up structure mounted on the surface of the aluminum plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connecting to the electrode pad. Besides, a method of manufacturing a carrier plate structure having a chip embedded therein is disclosed.

Abstract translation: 具有嵌入其中的芯片的载体板结构包括铝板，其具有从铝板的上表面延伸到下表面的多个通孔，其中形成有空腔，并且在铝板的表面上形成氧化铝层 ; 嵌入在所述腔中的芯片，其上设置有多个电极焊盘的有源表面; 以及至少一个堆积结构，其安装在所述铝板的表面和所述芯片的有源表面上，其中所述积聚结构包括至少一个导电结构以电连接到所述电极焊盘。 此外，公开了一种制造具有嵌入其中的芯片的载体板结构的方法。

公开(公告)号：US20080164597A1

公开(公告)日：2008-07-10

申请号：US11649295

申请日：2007-01-04

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

IPC: H01L23/48

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18162

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract translation: 具有嵌入其中的芯片的板结构包括其表面上形成有至少一个氧化铝层的铝板及其中的空腔; 嵌入在所述腔中的芯片，其中所述芯片具有活性表面; 安装在所述有源表面上的至少一个电极焊盘; 以及安装在铝板的表面，芯片的有源表面和电极焊盘的表面上的积聚结构，其中积聚结构包括至少一个电连接到电极焊盘的导电体。 此外，公开了一种制造具有嵌入其中的芯片的板结构的方法。 因此，具有嵌入其中的芯片的板结构可以通过简单的方法来加工，以实现铝的强度和氧化铝的刚性。

公开(公告)号：US20080116562A1

公开(公告)日：2008-05-22

申请号：US11984349

申请日：2007-11-16

Applicant: Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L21/58 ,  H01L23/02

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/18162

Abstract: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Abstract translation: 公开了一种用于半导体芯片的载体结构及其制造方法。 该方法包括以下步骤：提供具有至少一个通孔的载体板，其中在载体板的表面上形成可移除膜，并且半导体芯片通过可移除膜临时固定在通孔中; 用粘合剂材料填充载体板的通孔和半导体芯片之间的间隙以固定半导体芯片; 并移除可拆卸胶片。 所公开的方法可以减少半导体在腔内固定之前由抖动引起的微小偏移导致的对准误差，从而提高对准的精度，以便于精细布线，并且满足紧凑的趋势 半导体封装尺寸。

公开(公告)号：US20080030965A1

公开(公告)日：2008-02-07

申请号：US11701441

申请日：2007-02-02

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/00

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09509 ,  Y10T29/49126

Abstract: A circuit board structure with capacitor embedded therein and method for fabricating the same are disclosed, especially a core structure with capacitors embedded therein and method for fabricating the same. The structure comprising: a core board having a dielectric layer with a first surface and an opposite second surface; at least one high dielectric coefficient material layer formed in the dielectric layer, wherein a first electrode plate formed on the other surface of the high dielectric coefficient material layer; a first circuit layer formed on the first surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and having a second electrode plate corresponding to the first electrode plate; and a first conductive via formed in the dielectric layer and electrically connecting the first electrode plate and the first circuit layer.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法，特别是其中嵌有电容器的芯结构及其制造方法。 该结构包括：芯板，具有具有第一表面和相对的第二表面的电介质层; 形成在所述电介质层中的至少一个高介电系数材料层，其中形成在所述高介电系数材料层的另一个表面上的第一电极板; 形成在所述电介质层的第一表面上的第一电路层; 形成在电介质层的第二表面上并具有与第一电极板对应的第二电极板的第二电路层; 以及形成在电介质层中并电连接第一电极板和第一电路层的第一导电通孔。