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    Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof
    21.
    发明授权
    Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof 有权
    在形成集成电路场效应晶体管之前，通过在形成其栅极绝缘层之前执行多个注入来制造方法

    公开(公告)号：US6117715A

    公开(公告)日：2000-09-12

    申请号：US143131

    申请日：1998-08-28

    申请人： Dae-Won Ha

    发明人： Dae-Won Ha

    IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823412

    摘要： Multiple implants are performed in an integrated circuit substrate by implanting ions into a face thereof. Then, a gate insulating layer and a gate electrode are formed on the face of the integrated circuit substrate after performing the multiple implants in the integrated circuit substrate. Preferably, ions are not implanted into the integrated circuit substrate through the face after forming the gate insulating layer and the gate electrode on the face of the integrated circuit substrate. By preferably performing all implants prior to forming a gate insulating layer, the gate insulating layer is not degraded by implanting ions into the face of the integrated circuit substrate through the gate insulating layer.

    摘要翻译： 通过将离子注入其表面，在集成电路基板中执行多个植入。 然后，在集成电路基板中执行多个注入之后，在集成电路基板的表面上形成栅极绝缘层和栅电极。 优选地，在形成集成电路基板的表面上的栅极绝缘层和栅电极之后，离子不会通过面被注入到集成电路基板中。 通过优选在形成栅极绝缘层之前执行所有注入，通过通过栅极绝缘层将离子注入到集成电路基板的表面中，栅极绝缘层不会劣化。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICE
    23.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20120225504A1

    公开(公告)日：2012-09-06

    申请号：US13411678

    申请日：2012-03-05

    申请人： SANG-HYUN HONG ,  JUNG-HYUK LEE ,  SU-JIN AHN ,  DAE-WON HA

    发明人： SANG-HYUN HONG ,  JUNG-HYUK LEE ,  SU-JIN AHN ,  DAE-WON HA

    IPC分类号： H01L21/66

    CPC分类号： H01L22/14 ,  H01L22/20 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

    摘要翻译： 一种制造半导体器件的方法包括提供晶片，形成在晶片上包括相变材料层的存储器件，完成制造半导体器件的晶片级工艺，以及对晶片进行热处理以使相位致密化 换材料 为此，热处理的工艺温度高于相变材料的结晶温度，并且低于相变材料的熔点。

    Non-volatile memory devices including stacked NAND-type resistive memory cell strings
    24.
    发明授权
    Non-volatile memory devices including stacked NAND-type resistive memory cell strings 有权
    非易失性存储器件包括堆叠的NAND型电阻存储器单元串

    公开(公告)号：US08036018B2

    公开(公告)日：2011-10-11

    申请号：US12917175

    申请日：2010-11-01

    申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

    发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/00 ,  G11C5/06

    CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

    摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

    Phase change memory device having Schottky diode and method of fabricating the same
    25.
    发明授权
    Phase change memory device having Schottky diode and method of fabricating the same 有权
    具有肖特基二极管的相变存储器件及其制造方法

    公开(公告)号：US07804703B2

    公开(公告)日：2010-09-28

    申请号：US12120583

    申请日：2008-05-14

    申请人： Dae-Won Ha ,  Gi-Tae Jeong

    发明人： Dae-Won Ha ,  Gi-Tae Jeong

    IPC分类号： G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

    摘要翻译： 相变存储器件包括沿着半导体衬底上的方向延伸的字线。 低浓度半导体图案设置在字线上。 节点电极设置在低浓度半导体图案上。 肖特基二极管设置在低浓度半导体图案和节点电极之间。 相变电阻器设置在节点电极上。

    Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same
    26.
    发明申请
    Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same 有权
    具有凸起的半导体图案的有源元件的半导体器件及其制造方法

    公开(公告)号：US20090102012A1

    公开(公告)日：2009-04-23

    申请号：US12288280

    申请日：2008-10-17

    申请人： Dae-Won Ha ,  Sang-Yoon Kim

    发明人： Dae-Won Ha ,  Sang-Yoon Kim

    IPC分类号： H01L27/082

    CPC分类号： H01L27/0629 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635

    摘要： A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element;hole on the second exposed portion of the semiconductor region. A surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate may have a same conductivity type. Related methods are also discussed.

    摘要翻译： 半导体器件可以包括半导体衬底的半导体区域，其中在半导体区域和半导体衬底的主体之间限定P-N结。 半导体衬底中的绝缘隔离结构可以围绕半导体区域的侧壁。 层间绝缘层可以在半导体衬底上，半导体区域上和绝缘隔离结构上，并且层间绝缘层可以具有暴露半导体区域的相应第一和第二部分的第一和第二间隔开的元件孔。 第一半导体图案可以位于半导体区域的第一暴露部分的第一元件孔中，并且第二半导体图案可以在第二元件中;半导体区域的第二暴露部分上的孔。 与半导体衬底相对的第一半导体图案的表面部分和与半导体衬底相对的第二半导体图案的表面部分可以具有相同的导电类型。 还讨论了相关方法。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING RESISTORS
    27.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING RESISTORS 有权
    制造具有电阻器的半导体器件的方法

    公开(公告)号：US20090098703A1

    公开(公告)日：2009-04-16

    申请号：US12248470

    申请日：2008-10-09

    申请人： Dae-Won Ha ,  Sang-Yoon Kim

    发明人： Dae-Won Ha ,  Sang-Yoon Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

    摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

    摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

    Semiconductor device and method of fabricating the same
    29.
    发明申请
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20080179648A1

    公开(公告)日：2008-07-31

    申请号：US12000504

    申请日：2007-12-13

    申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

    发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

    摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

    摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。