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    Anti-fuse circuit and method of operation
    21.
    发明授权
    Anti-fuse circuit and method of operation 失效
    防熔丝电路及操作方法

    公开(公告)号：US06597234B2

    公开(公告)日：2003-07-22

    申请号：US10017429

    申请日：2001-12-14

    申请人： Douglas M. Reber ,  Stephen R. Crown

    发明人： Douglas M. Reber ,  Stephen R. Crown

    IPC分类号： H01H3776

    CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its non-conductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.

    摘要翻译： 用于实现存储器中冗余的反熔丝利用通常被认为是不期望的以提供两个容易检测状态的正常晶体管特性。 非编程状态，即高阻抗状态，简单地用非导通状态的正常晶体管实现。 通过强制正常晶体管将电流传导通过其栅极来实现低阻状态的编程状态。 这导致栅极电介质变得永久导电。 然后，该编程晶体管在其源极和漏极之间是导电的，其容易与保持在其非导通状态的晶体管区分开。 结果是采用了一种使用反熔丝的保险丝技术，可以通过电气编程而不是通过激光编程实现轻松区分编程和非编程状态。

    Integrated circuit having interconnect to a substrate and method therefor
    22.
    发明授权
    Integrated circuit having interconnect to a substrate and method therefor 失效
    具有与衬底互连的集成电路及其方法

    公开(公告)号：US06555915B1

    公开(公告)日：2003-04-29

    申请号：US09986232

    申请日：2001-10-22

    申请人： Douglas M. Reber

    发明人： Douglas M. Reber

    IPC分类号： H01L2940

    CPC分类号： H01L21/76895 ,  H01L21/76838 ,  H01L21/823475

    摘要： A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.

    摘要翻译： 源极/漏极和栅极之间的接触通过使栅极电介质的选定部分通过植入物导电到该栅极电介质的该选定部分来进行。 栅极材料位于整个集成电路的一层中。 栅极连接到源极/漏极的区域被识别，并且植入那些识别位置处的栅极电介质以使其导电。 源极/漏极形成为使得它们在导电栅极电介质的这些区域下方延伸，使得在这些位置处，注入的栅极电介质将栅极短路到源极/漏极。 这节省了集成电路上的区域，减少了对互连层的需求，并且避免了在暴露的硅衬底上沉积和蚀刻多晶硅相关的问题。

    Stress migration mitigation
    24.
    发明授权
    Stress migration mitigation 有权
    压力迁移缓解

    公开(公告)号：US09122829B2

    公开(公告)日：2015-09-01

    申请号：US13956044

    申请日：2013-07-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F2217/76 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.

    摘要翻译： 配置半导体器件的计算机实现的方法包括识别具有大于半导体器件的应力引起的空隙形成特征长度的互连路径长度的互连，以及与处理器相邻配置的导电结构，以定义 互连的一对段。 每个段的长度不大于互连的应力诱导的空隙形成特征长度，并且导电结构选自连接到互连的诱饵通道，沿互连设置的浮动瓦， 横向地从互连件向外延伸，并且从其中布置有互连的第一金属层的跳线到第二金属层。

    METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE
    26.
    发明申请
    METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE 有权
    形成包装半导体器件的方法

    公开(公告)号：US20150061709A1

    公开(公告)日：2015-03-05

    申请号：US14011160

    申请日：2013-08-27

    申请人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    发明人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L22/32 ,  H01L23/5226 ,  H01L24/19 ,  H01L2224/13

    摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

    摘要翻译： 制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。 互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。 一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。 通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。 将管芯载体分离以形成多个封装的半导体器件。 在分离模具载体期间移除探针焊盘组。

    FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING
    27.
    发明申请
    FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING 有权
    使用互连和VIAS的熔断器/电阻器及其制造方法

    公开(公告)号：US20140353797A1

    公开(公告)日：2014-12-04

    申请号：US13907497

    申请日：2013-05-31

    申请人： Mehul D. SHROFF ,  Douglas M. REBER ,  Edward O. TRAVIS

    发明人： Mehul D. SHROFF ,  Douglas M. REBER ,  Edward O. TRAVIS

    IPC分类号： H01L23/525 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

    摘要翻译： 一种半导体结构，包括在具有衬底的功能层上的熔丝/电阻器结构。 熔丝/电阻器结构包括通孔，第一互连层和第二互连层。 通孔在功能层之上，并且具有与第一端垂直相对的第一端和第二端，其中第一端由第一边缘和与第一边缘相对的第二边缘限定，第二端由第三边缘 以及与第三边缘相对的第四边缘。 第一互连层包括水平延伸并接触第一端并从第一边缘到第二边缘完全延伸的第一金属层。 第二互连层包括水平延伸并接触通孔的第二端并延伸超过第三边缘但到达不到第四边缘的一半的第二金属层。

    Semiconductor device having a nanotube layer and method for forming
    28.
    发明授权
    Semiconductor device having a nanotube layer and method for forming 有权
    具有纳米管层的半导体器件及其形成方法

    公开(公告)号：US08883639B2

    公开(公告)日：2014-11-11

    申请号：US13358137

    申请日：2012-01-25

    申请人： Douglas M. Reber

    发明人： Douglas M. Reber

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53276 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.

    摘要翻译： 形成半导体器件的方法包括在衬底上形成第一导电层。 具有第一开口的介电层形成在第一导电层上。 种子层沉积在第一介电层上和第一开口中。 一层由导电纳米管从第一介电层上的种子层和第一开口形成。 在导电纳米管层上形成第二电介质。 在第一开口上的第二电介质层中形成开口。 导电材料沉积在第二个开口中。

    Semiconductor device with embedded heat spreading
    29.
    发明授权
    Semiconductor device with embedded heat spreading 有权
    具有嵌入式散热的半导体器件

    公开(公告)号：US08796841B2

    公开(公告)日：2014-08-05

    申请号：US13442014

    申请日：2012-04-09

    申请人： Edward O. Travis ,  Douglas M. Reber ,  Mehul D. Shroff

    发明人： Edward O. Travis ,  Douglas M. Reber ,  Mehul D. Shroff

    IPC分类号： H01L23/10

    CPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/3677 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

    摘要翻译： 半导体器件包括半导体衬底和多个时钟驱动器，其中多个时钟驱动器包括半导体器件的基本上所有的时钟驱动器，以及半导体衬底上的互连区域，其中互连区域包括多个散热器， 其中所述多个时钟驱动器中的至少25％具有所述多个散热器中相应的散热器。 多个散热器的每个相应的散热器覆盖多个时钟驱动器的对应的时钟驱动器内的至少50％的晶体管，并延伸到对应的时钟驱动器内的晶体管的周边的至少70％。

    Semiconductor device with vias on a bridge connecting two buses
    30.
    发明授权
    Semiconductor device with vias on a bridge connecting two buses 有权
    半桥设备，通孔连接两条总线桥

    公开(公告)号：US08736071B2

    公开(公告)日：2014-05-27

    申请号：US13285073

    申请日：2011-10-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L23/48

    CPC分类号： G06F13/4027 ,  G06F17/5077 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

    摘要翻译： 半导体器件包括导电总线和导电桥。 相应的导电桥与至少一个导电总线的至少两个部分导电耦合。 当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度 所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。