公开(公告)号：US06797957B2

公开(公告)日：2004-09-28

申请号：US10097405

申请日：2002-03-15

Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

IPC: H01L3702

CPC classification number: H01L37/02

Abstract: An infrared detection element having a single-crystalline base layer 3 with a thickness of 50 nm to 10 &mgr;m having a principal surface, a first electrode layer 4 formed on the principal surface of the single-crystalline base layer 3, a ferroelectric layer 5 which is formed on the first electrode layer 4 and is composed of a single-crystalline layer or a unidirectionally oriented layer. Distortion of the single-crystalline layer or a unidirectionally oriented layer in a surface parallel to the principal surface of the single-crystalline base layer 3 is elastically constrained by the single-crystalline base layer 3. The infrared detection element further has a second electrode layer 6 formed on the ferroelectric layer 5. An amount of charge varies with changes in temperature caused by irradiation of infrared light to the ferroelectric layer 5.

Abstract translation: 具有厚度为50nm〜10μm的具有主面的单晶基底层3的红外线检测元件，形成在单晶基底层3的主面上的第一电极层4，强电介质层5 形成在第一电极层4上，由单晶层或单向取向层构成。 在与单晶基底层3的主表面平行的表面中的单晶层或单向取向层的失真由单晶基底层3弹性约束。红外线检测元件还具有第二电极层 形成在铁电层5上。电荷量随着红外光照射到铁电层5而引起的温度变化。

公开(公告)号：US06533906B2

公开(公告)日：2003-03-18

申请号：US09795479

申请日：2001-03-01

Applicant: Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

Inventor： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

IPC: C23C1434

CPC classification number: C23C14/345 ,  C23C14/0068 ,  C23C14/088 ,  C23C14/3407 ,  C23C14/352 ,  C30B23/02 ,  C30B29/22 ,  C30B29/32 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L28/55

Abstract: A method of manufacturing an epitaxially-strained lattice film of an oxide, in which epitaxially-strained lattices having a good crystalline property are formed by applying RF power to a substrate holder and irradiating positive ions having a moderate energy while preventing damage to the strained lattice film to be stacked by oxygen negative ions. This method simultaneously overcomes both the problem of damage to the film by irradiation of oxygen negative ions, which is peculiar to sputtering of oxides, and the problem of failure to strain due to relaxation of the strain during deposition.

Abstract translation: 制造具有良好结晶特性的外延应变晶格的氧化物的外延应变晶格膜的方法通过向衬底保持器施加RF功率并照射具有中等能量的正离子而形成，同时防止对应变晶格的损伤 膜由氧负离子堆叠。 该方法同时克服了通过照射氧负离子（这是氧化物溅射所特有的）对膜的损坏的问题，以及由于沉积期间的应变松弛而导致的不能应变的问题。

公开(公告)号：US06455430B2

公开(公告)日：2002-09-24

申请号：US09431181

申请日：1999-11-01

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21302

CPC classification number: H01L21/76802 ,  H01L21/3146 ,  H01L21/3212 ,  H01L21/7684

Abstract: A carbon film is formed over an insulating film and a contact hole is defined therein by patterning. Copper is formed over an entire surface including the contact hole and polished by chemical mechanical polishing. The polishing of the copper is terminated with the carbon film as an etching stopper thereby to allow the copper to remain in the contact hole alone, whereby an embedded interconnection made up of the copper is formed by a damascene method.

Abstract translation: 在绝缘膜上形成碳膜，通过图案化形成接触孔。 铜在包括接触孔的整个表面上形成并通过化学机械抛光抛光。 用碳膜作为蚀刻停止器终止铜的抛光，从而允许铜单独留在接触孔中，由此通过镶嵌法形成由铜构成的嵌入式互连。

公开(公告)号：US6103618A

公开(公告)日：2000-08-15

申请号：US346943

申请日：1999-07-02

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76885

Abstract: A method for forming an interconnection in a semiconductor element includes a process for forming a groove on an underlying substrate so as to correspond to the designed pattern of the interconnection. An underlayer for improving crystalline orientation of the interconnection is formed on the underlying substrate having the groove. A thin film of interconnection material is formed in the groove and a heattreatment process is carried out to ensure that the groove is filled with the thin film of the interconnection material. Formation of the interconnection is completed by polishing the surface of the thin film by a predetermined quantity.

Abstract translation: 在半导体元件中形成互连的方法包括在下面的基底上形成与所设计的互连图案对应的凹槽的工艺。 用于改善互连结晶取向的底层形成在具有凹槽的底层基底上。 在槽中形成互连材料的薄膜，并进行热处理工艺，以确保槽被互连材料的薄膜填充。 通过以预定量抛光薄膜的表面来完成互连的形成。

公开(公告)号：US5889299A

公开(公告)日：1999-03-30

申请号：US804394

申请日：1997-02-21

Applicant: Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

Inventor： Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

IPC: H01L21/02 ,  H01L29/76

CPC classification number: H01L28/55

Abstract: A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.

Abstract translation: 一种薄膜电容器，包括在其表面上具有立方体系的（100）面或四方晶系的（001）面的第一电极，在第一电极上外延生长并呈现出固有地属于 立方体的钙钛矿结构，以及形成在电介质薄膜上的第二电极。 此外，电介质薄膜满足以下关系V / V0 / = 1.01，其中属于立方体系的真实钙钛矿晶体结构的单位晶格体积（晶格常数a0）由V0 = a03表示，单位晶格体积 晶格常数a = b NOTEQUAL c），其外延生长后由V = a2c表示为四方晶系，并满足以下关系c / a> / = 1.01其中c / a表示晶格常数 在膜的厚度方向上的“c”和与膜的平面平行的方向上的晶格常数“a”。

公开(公告)号：US5670808A

公开(公告)日：1997-09-23

申请号：US591153

申请日：1996-01-25

Applicant: Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

Inventor： Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/095 ,  H01L29/92 ,  H01L27/108

CPC classification number: H01L27/0629 ,  H01L27/0605 ,  H01L27/10852 ,  H01L28/40

Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Abstract translation: 其中SiO 2膜和第一布线层依次布置在GaAs衬底上的半导体器件。 在第一布线层上形成电容器。 电容器包括从下侧依次具有由Ti层，Mo层和Pt层构成的多层结构的下电极。 电容器还包括由钛酸锶制成的电介质膜。 电容器还包括从下侧依次具有由WNx层（120μm）和W层（300nm）组成的多层结构的上部电极。 与电介质膜接触的上电极的表面由氮化钨层限定。

公开(公告)号：US08305147B2

公开(公告)日：2012-11-06

申请号：US13424591

申请日：2012-03-20

Applicant: Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

Inventor： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

IPC: H03F3/14

CPC classification number: H03F3/19 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H03F3/245

Abstract: A power amplifier according to the embodiments includes: a silicon substrate; an input terminal configured to receive an input of a RF signal; a power dividing unit configured to divide the RF signal into a first signal and a second signal; a phase modulating unit configured to modulate a phase of the second signal; an N well formed in the silicon substrate; a P well formed in the N well and configured to receive an input of the second signal of a modulated phase; a gate insulating film formed on the P well; a gate electrode formed on the gate insulating film and configured to receive an input of the first signal; source and drain electrodes formed on both sides of the gate electrode in the silicon substrate; and an output terminal configured to output a RF signal obtained from the drain electrode.

Abstract translation: 根据实施例的功率放大器包括：硅衬底; 输入终端，被配置为接收RF信号的输入; 功率分配单元，被配置为将RF信号划分为第一信号和第二信号; 相位调制单元，被配置为调制所述第二信号的相位; 在硅衬底中形成N阱; P阱形成在N阱中并且被配置为接收调制相位的第二信号的输入; 在P阱上形成栅极绝缘膜; 栅电极，形成在所述栅极绝缘膜上并被配置为接收所述第一信号的输入; 源极和漏极形成在硅衬底中的栅电极的两侧; 以及输出端子，被配置为输出从漏电极获得的RF信号。

公开(公告)号：US20120241877A1

公开(公告)日：2012-09-27

申请号：US13220116

申请日：2011-08-29

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

IPC: H01L29/84

CPC classification number: H03J3/20 ,  H03B5/326 ,  H03H9/02566

Abstract: According to one embodiment, an acoustic semiconductor device includes an element unit, and a first terminal. The element unit includes an acoustic resonance unit. The acoustic resonance unit includes a semiconductor crystal. An acoustic standing wave is excitable in the acoustic resonance unit and is configured to be synchronously coupled with electric charge density within at least one portion of the semiconductor crystal via deformation-potential coupling effect. The first terminal is electrically connected to the element unit. At least one selected from outputting and inputting an electrical signal is implementable via the first terminal. The electrical signal is coupled with the electric charge density. The outputting the electrical signal is from the acoustic resonance unit, and the inputting the electrical signal is into the acoustic resonance unit.

Abstract translation: 根据一个实施例，声学半导体器件包括元件单元和第一端子。 元件单元包括声共振单元。 声共振单元包括半导体晶体。 声驻波在声共振单元中是可兴奋的，并且被配置为通过变形电势耦合效应与半导体晶体的至少一部分内的电荷密度同步耦合。 第一端子电连接到元件单元。 从输出和输入电信号中选出的至少一个可经由第一终端实现。 电信号与电荷密度耦合。 输出电信号来自声共振单元，并且输入电信号进入声共振单元。

公开(公告)号：US20120235246A1

公开(公告)日：2012-09-20

申请号：US13425735

申请日：2012-03-21

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC: H01L27/088

CPC classification number: H03F1/02 ,  H01L27/105 ,  H03F1/32 ,  H03F3/211 ,  H03F2200/432

Abstract: One embodiment of a semiconductor device provided with a semiconductor substrate, a device region formed on the semiconductor substrate, a device isolation region, which encloses the device region, a plurality of first gate electrodes arranged so as to be parallel to each other on the device region and electrically connected to each other, and a plurality of second gate electrodes arranged so as to be parallel to a plurality of first gate electrodes on the device region and electrically connected to each other, wherein the first gate electrode is arranged so as to be interposed between the second gate electrodes, a gate width of the first gate electrode is smaller than the gate width of the second gate electrode, and a DC bias voltage higher than that of the second gate electrode is applied to the first gate electrode.

Abstract translation: 设置有半导体衬底的半导体器件的一个实施例，形成在半导体衬底上的器件区域，封装器件区域的器件隔离区域，在器件上彼此平行布置的多个第一栅极电极 并且彼此电连接;以及多个第二栅电极，其被布置成与所述器件区域上的多个第一栅极平行并且彼此电连接，其中所述第一栅电极被布置为 插入在第二栅电极之间，第一栅电极的栅极宽度小于第二栅电极的栅极宽度，并且将高于第二栅电极的直流偏置电压施加到第一栅电极。

公开(公告)号：US08039873B2

公开(公告)日：2011-10-18

申请号：US12276787

申请日：2008-11-24

Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC: H01L27/105

CPC classification number: H01L27/088 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes.

Abstract translation: 半导体器件包括：衬底，其包括具有由多个边缘限定的多边形形状的元件区域和围绕该元件区域的隔离区域;以及多个栅电极，设置在该衬底上，与该元件区域交叉，与该 彼此电连接，其中至少一个边缘不与任何栅电极交叉，并且不平行于栅电极。