公开(公告)号：US07348217B2

公开(公告)日：2008-03-25

申请号：US11523110

申请日：2006-09-18

Applicant: Mauro J. Kobrinsky ,  R. Scott List ,  Sarah E. Kim ,  Michael C. Harmes

Inventor： Mauro J. Kobrinsky ,  R. Scott List ,  Sarah E. Kim ,  Michael C. Harmes

IPC: H01L21/00

CPC classification number: H01L24/11 ,  H01L21/304 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/31 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/29099

Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.

Abstract translation: 公开了在金属接触界面处优化和控制扩散蠕变的方法和结构。 本发明的实施例可适应相邻触点中的高度变化，降低平坦化均匀性要求，并且通过采用对压缩接口负载可预测地响应的形状和材料来促进在较低温度和压力下的接触接合。

公开(公告)号：US07084495B2

公开(公告)日：2006-08-01

申请号：US10687127

申请日：2003-10-16

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L23/34

CPC classification number: F04B17/00 ,  F04B19/006 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06589 ,  H01L2924/01322

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract translation: 一组发热集成电路芯片可以设置有中间冷却集成电路芯片。 冷却集成电路芯片可以包括用于冷却流体流动的微通道。 可以使用集成的电渗泵泵送冷却流体。 在一些实施方案中，使用集成的重组合器可以实现冷却流体气体的去除。

公开(公告)号：US06992381B2

公开(公告)日：2006-01-31

申请号：US10698749

申请日：2003-10-31

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

IPC: H01L23/34

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

公开(公告)号：US06897125B2

公开(公告)日：2005-05-24

申请号：US10665824

申请日：2003-09-17

Applicant: Patrick Morrow ,  R. Scott List ,  Sarah E. Kim

Inventor： Patrick Morrow ,  R. Scott List ,  Sarah E. Kim

IPC: H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L21/30

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01082

Abstract: Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.

Abstract translation: 公开了在晶片叠层上形成背面连接的各种方法。 为了形成背面连接，通孔形成在要与第二晶片结合的第一晶片中。 用于背面连接的通路与互连结构一起形成在第一晶片的一侧，并且使用这些通孔在第一晶片的相对侧上形成背面连接。

公开(公告)号：US06870270B2

公开(公告)日：2005-03-22

申请号：US10334172

申请日：2002-12-28

Applicant: Mauro J. Kobrinsky ,  R. Scott List ,  Sarah E. Kim ,  Michael C. Harmes

Inventor： Mauro J. Kobrinsky ,  R. Scott List ,  Sarah E. Kim ,  Michael C. Harmes

IPC: H01L21/304 ,  H01L21/60 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L21/304 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/31 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/29099

Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.

公开(公告)号：US06861274B2

公开(公告)日：2005-03-01

申请号：US10402435

申请日：2003-03-28

Applicant: R. Scott List ,  Alan Myers ,  Quat T. Vu

Inventor： R. Scott List ,  Alan Myers ,  Quat T. Vu

IPC: F04B17/00 ,  F04B19/00 ,  H01L21/00

CPC classification number: F04B17/00 ,  F04B19/006

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract translation: 可以使用具有纳米多孔开孔电介质玻璃料的半导体加工技术制造电渗泵。 这种玻璃料可能导致具有更好泵送能力的电渗泵。

公开(公告)号：US06833321B2

公开(公告)日：2004-12-21

申请号：US10001305

申请日：2001-11-30

Applicant: Stefan Hau-Riege ,  R. Scott List

Inventor： Stefan Hau-Riege ,  R. Scott List

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract translation: 描述制造半导体器件的方法。 该方法包括形成接触通孔的导电层，使得导电层在远离通孔的地方包括较高浓度的通孔附近的掺杂剂的电迁移量。

公开(公告)号：US06661085B2

公开(公告)日：2003-12-09

申请号：US10066668

申请日：2002-02-06

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L2302

CPC classification number: H01L24/10 ,  H01L23/481 ,  H01L23/585 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

公开(公告)号：US07723208B2

公开(公告)日：2010-05-25

申请号：US10669205

申请日：2003-09-24

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L21/30

CPC classification number: F04B19/006 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/00

Abstract: Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.

Abstract translation: 沟槽可以形成在一对晶片的上表面中。 每个沟槽可以涂覆有能够在利用用于泵送的电渗效应的系统中用于冷却的流体中除去氧气或氢气的催化剂。 可以形成通道以将流体与涂覆有催化剂的沟槽连通。 基板可以以面对面邻接方式组合，例如使用铜 - 铜键合来形成再组合器。

公开(公告)号：US07227257B2

公开(公告)日：2007-06-05

申请号：US10315565

申请日：2002-12-09

Applicant: Sarah E. Kim ,  R. Scott List ,  Alan Myers

Inventor： Sarah E. Kim ,  R. Scott List ,  Alan Myers

IPC: H01L23/34 ,  H01L23/10

CPC classification number: H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract translation: 本公开一般涉及微电子技术，更具体地，涉及用于利用微通道或微沟槽冷却有源电子器件的装置及其制造技术。