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公开(公告)号：US07348217B2
公开(公告)日：2008-03-25
申请号：US11523110
申请日：2006-09-18
IPC分类号： H01L21/00
CPC分类号： H01L24/11 , H01L21/304 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/31 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/10135 , H01L2224/10165 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13022 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/81136 , H01L2224/81141 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/8182 , H01L2225/06513 , H01L2225/06593 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/29099
摘要： Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
摘要翻译： 公开了在金属接触界面处优化和控制扩散蠕变的方法和结构。 本发明的实施例可适应相邻触点中的高度变化，降低平坦化均匀性要求，并且通过采用对压缩接口负载可预测地响应的形状和材料来促进在较低温度和压力下的接触接合。
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公开(公告)号：US06870270B2
公开(公告)日：2005-03-22
申请号：US10334172
申请日：2002-12-28
IPC分类号： H01L21/304 , H01L21/60 , H01L23/02 , H01L23/48 , H01L23/52 , H01L25/065 , H01L29/40
CPC分类号： H01L24/11 , H01L21/304 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/31 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/10135 , H01L2224/10165 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13022 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/81136 , H01L2224/81141 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/8182 , H01L2225/06513 , H01L2225/06593 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/29099
摘要： Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
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公开(公告)号：US06790748B2
公开(公告)日：2004-09-14
申请号：US10326206
申请日：2002-12-19
申请人： Sarah E. Kim , R. Scott List , Mauro J. Kobrinsky
发明人： Sarah E. Kim , R. Scott List , Mauro J. Kobrinsky
IPC分类号： H01L2176
CPC分类号： H01L25/50 , H01L21/304 , H01L23/481 , H01L25/0657 , H01L29/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/13023 , H01L2224/131 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/15311 , Y10S438/977 , H01L2924/014 , H01L2224/05599
摘要： Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.
摘要翻译： 在堆叠的微电子器件的制造中，用于薄化晶片到晶片垂直叠层的方法。 这些方法包括在垂直堆叠中物理去除待稀释的晶片的未支撑部分。 未支撑部分的去除基本上消除了晶片的潜在的破裂和碎裂，当存在未支撑的部分时，这可能在稀化过程中发生。
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4.发明授权Method of signal distribution based on a standing wave within a closed loop path 失效基于闭环路径内驻波的信号分配方法公开(公告)号：US07120817B2
公开(公告)日：2006-10-10
申请号：US10447706
申请日：2003-05-29
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.
摘要翻译： 基于闭环的定时信号分配架构包括耦合到以闭环布置设置的信号路径的至少一个信号源，以便于在信号路径内产生驻波信号。 在一个实施例中，至少一个接收器耦合到信号路径，以基于驻波信号产生至少一个数字时钟信号。
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公开(公告)号：US07723208B2
公开(公告)日：2010-05-25
申请号：US10669205
申请日：2003-09-24
申请人： Sarah E. Kim , R. Scott List , James G. Maveety , Alan M. Myers , Quat T. Vu
发明人： Sarah E. Kim , R. Scott List , James G. Maveety , Alan M. Myers , Quat T. Vu
IPC分类号： H01L21/30
CPC分类号： F04B19/006 , H01L23/473 , H01L2224/16 , H01L2224/73253 , H01L2924/01078 , H01L2924/10253 , H01L2924/00
摘要： Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.
摘要翻译： 沟槽可以形成在一对晶片的上表面中。 每个沟槽可以涂覆有能够在利用用于泵送的电渗效应的系统中用于冷却的流体中除去氧气或氢气的催化剂。 可以形成通道以将流体与涂覆有催化剂的沟槽连通。 基板可以以面对面邻接方式组合，例如使用铜 - 铜键合来形成再组合器。
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公开(公告)号：US07227257B2
公开(公告)日：2007-06-05
申请号：US10315565
申请日：2002-12-09
申请人： Sarah E. Kim , R. Scott List , Alan Myers
发明人： Sarah E. Kim , R. Scott List , Alan Myers
CPC分类号： H01L23/473 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.
摘要翻译： 本公开一般涉及微电子技术，更具体地，涉及用于利用微通道或微沟槽冷却有源电子器件的装置及其制造技术。
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7.发明授权Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration 失效使用柔性膀胱压力机进行三维（3D）垂直堆叠集成的晶片贴合公开(公告)号：US07037804B2
公开(公告)日：2006-05-02
申请号：US10695328
申请日：2003-10-27
申请人： Scot A. Kellar , Sarah E. Kim , R. Scott List
发明人： Scot A. Kellar , Sarah E. Kim , R. Scott List
CPC分类号： H01L25/50 , H01L21/185 , H01L21/743 , H01L21/76898 , H01L24/12 , H01L24/16 , H01L24/72 , H01L24/75 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13099 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16 , H01L2224/2919 , H01L2224/75315 , H01L2224/81203 , H01L2224/81894 , H01L2224/81895 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/0665 , H01L2924/00014
摘要： A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
摘要翻译： 三维（3-D）集成芯片系统设置有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置沉积在第一和第二晶片的相对表面上的金属粘结层，以在第一和第二晶片上的有源IC器件之间建立电连接，并且当第一晶片为 使用柔性膀胱压力机压在第二晶片上，以考虑穿过第一和第二晶片的相对表面的金属粘合层的高度差异。
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公开(公告)号：US07034394B2
公开(公告)日：2006-04-25
申请号：US10682137
申请日：2003-10-08
IPC分类号： H01L23/34
CPC分类号： H01L35/32 , H01L23/38 , H01L23/50 , H01L24/11 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L27/16 , H01L2224/05001 , H01L2224/13099 , H01L2224/16145 , H01L2224/451 , H01L2224/48091 , H01L2224/48471 , H01L2224/73253 , H01L2224/73257 , H01L2224/81801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01051 , H01L2924/01052 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15312 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要： A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.
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9.发明授权Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips 失效用中间冷却集成电路芯片形成一堆发热集成电路芯片的方法公开(公告)号：US07696015B2
公开(公告)日：2010-04-13
申请号：US11448232
申请日：2006-06-07
申请人： Sarah E. Kim , R. Scott List , James G. Maveety , Alan M. Myers , Quat T. Vu
发明人： Sarah E. Kim , R. Scott List , James G. Maveety , Alan M. Myers , Quat T. Vu
CPC分类号： F04B17/00 , F04B19/006 , H01L23/473 , H01L25/0657 , H01L2224/16225 , H01L2225/06589 , H01L2924/01322
摘要： A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.
摘要翻译： 一组发热集成电路芯片可以设置有中间冷却集成电路芯片。 冷却集成电路芯片可以包括用于冷却流体流动的微通道。 可以使用集成的电渗泵泵送冷却流体。 在一些实施方案中，使用集成的重组合器可以实现冷却流体气体的去除。
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10.发明授权Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack 有权通过蚀刻在三维（3-D）晶圆到晶片垂直堆叠中的硅（Si）蚀刻停止层公开(公告)号：US07615462B2
公开(公告)日：2009-11-10
申请号：US11528986
申请日：2006-09-27
申请人： Sarah E. Kim , R. Scott List , Tom Letson
发明人： Sarah E. Kim , R. Scott List , Tom Letson
CPC分类号： H01L21/30604 , H01L21/3065 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/8182 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/30107
摘要： A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
摘要翻译： 在垂直堆叠的晶片中形成硅（Si）通孔的方法设置有从顶部晶片的选定金属线和在接触插塞之前形成的蚀刻停止层延伸的接触插塞。 这种方法包括选择性地蚀刻通过顶部晶片的硅（Si），直到被蚀刻停止层阻止以形成Si通孔; 沉积氧化物层以使Si通孔的侧壁绝缘; 在氧化物层和Si通孔的底部形成阻挡层; 以及将导电金属沉积到Si通孔中以提供位于垂直堆叠的晶片上的有源IC器件与外部互连之间的电连接。
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