公开(公告)号：US06750471B2

公开(公告)日：2004-06-15

申请号：US10205529

申请日：2002-07-25

Applicant: Donald Stimson Bethune ,  Sandip Tiwari

Inventor： Donald Stimson Bethune ,  Sandip Tiwari

IPC: H01L3524

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0014 ,  G11C23/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0046 ,  H01L51/0541 ,  H01L51/0545 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/943

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract translation: 本发明涉及一种微电子器件，特别是一种场效应晶体管，其包括源极，漏极，沟道，覆盖所述沟道的绝缘层，所述绝缘层包含至少一个闭合笼状分子，所述封闭笼分子能够表现出库仑阻塞效应 在所述源极和漏极之间施加电压。 描述了包含封闭笼分子，逻辑单元和存储单元的两种不同的微电子器件。

公开(公告)号：US06534819B2

公开(公告)日：2003-03-18

申请号：US09943210

申请日：2001-08-30

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L2976

CPC classification number: H01L21/76254 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/1203 ,  Y10S257/903

Abstract: A two transistor programmable logic cell 100 is used in programmable logic devices. The cell 100 has a backgate 3 that holds charge to program one of the two transistors into a logic 1 or a logic 0 state. Programmable logic devices are scalable to fine geometries and high densities and may be programmed to perform multiple logic functions on the same substrate.

公开(公告)号：US06333532B1

公开(公告)日：2001-12-25

申请号：US09356295

申请日：1999-07-16

Applicant: Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

Inventor： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC: H01L27108

CPC classification number: H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Abstract translation: 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了在形成SOI上的合并逻辑区域的同时形成具有在体Si中的深沟槽的存储电容器形成DRAM的问题。

公开(公告)号：US5937295A

公开(公告)日：1999-08-10

申请号：US947283

申请日：1997-10-07

Applicant: Wei Chen ,  Theoren Perlee Smith, III ,  Sandip Tiwari

Inventor： Wei Chen ,  Theoren Perlee Smith, III ,  Sandip Tiwari

IPC: H01L27/10 ,  B82B1/00 ,  G11C11/56 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0408 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7888 ,  G11C2216/08 ,  Y10S438/962

Abstract: A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in electron or hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Abstract translation: 一种存储装置和存储器，其中包括多个存储器件，其中每个存储器件具有间隔开的源极和漏极区，通道，阻挡绝缘层，纳米晶体或多个纳米晶体，控制势垒层和栅极 电极。 可以是量子点的纳米晶体在室温下存储一个电子或空穴或离散数量的电子或空穴，以为电子或空穴存储的每个变化提供超过热电压的阈值电压偏移。 本发明利用库仑阻塞将一个或多个存储的电子或空穴静电耦合到通道，同时避免路径中的库仑阻塞控制传导以感测存储的电荷。

公开(公告)号：US5757038A

公开(公告)日：1998-05-26

申请号：US554558

申请日：1995-11-06

Applicant: Sandip Tiwari ,  Samuel Jonas Wind

Inventor： Sandip Tiwari ,  Samuel Jonas Wind

IPC: H01L21/336 ,  H01L29/786 ,  H01L31/0328 ,  H01L29/80 ,  H01L31/0336

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/66666 ,  H01L29/78609 ,  H01L29/78642 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/7613 ,  H01L29/775

Abstract: A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.

Abstract translation: 具有基本上均匀宽度的超薄通道的双栅场效应晶体管通过自对准工艺形成，其利用不同材料之间的选择性蚀刻或受控氧化形成在源区和漏区之间延伸的垂直沟道，其厚度范围为 2.5nm至100nm。

公开(公告)号：US5739057A

公开(公告)日：1998-04-14

申请号：US634342

申请日：1996-04-18

Applicant: Sandip Tiwari ,  Samuel Jonas Wind

Inventor： Sandip Tiwari ,  Samuel Jonas Wind

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/338

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/66666 ,  H01L29/78609 ,  H01L29/78642 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/7613 ,  H01L29/775

Abstract: A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.

Abstract translation: 具有基本上均匀宽度的超薄通道的双栅场效应晶体管通过自对准工艺形成，其利用不同材料之间的选择性蚀刻或受控氧化形成在源区和漏区之间延伸的垂直沟道，其厚度范围为 2.5nm至100nm。

公开(公告)号：US5162891A

公开(公告)日：1992-11-10

申请号：US725589

申请日：1991-07-03

Applicant: Jeremy H. Burroughes ,  Mark S. Milshtein ,  Michael A. Tischler ,  Sandip Tiwari ,  Steven L. Wright

Inventor： Jeremy H. Burroughes ,  Mark S. Milshtein ,  Michael A. Tischler ,  Sandip Tiwari ,  Steven L. Wright

IPC: H01L31/10 ,  H01L31/0224 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

Abstract: A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.

Abstract translation: 公开了具有相反导电类型的自对准梯度接触扩散区域的侧向注入组III-V异质结构器件和制造这种器件的方法。 该器件包括由较低带隙III-V化合物半导体上形成的较高带隙III-V化合物半导体形成的异质结。 本发明的方法允许相反的导电型扩散区域同时扩散并穿透异质结。 这导致在扩散区域中形成异质结的化合物半导体材料的组成混合。

公开(公告)号：US5158896A

公开(公告)日：1992-10-27

申请号：US819093

申请日：1992-01-09

Applicant: Jeremy H. Burroughes ,  Mark S. Milshtein ,  Michael A. Tischler ,  Sandip Tiwari ,  Steven L. Wright

Inventor： Jeremy H. Burroughes ,  Mark S. Milshtein ,  Michael A. Tischler ,  Sandip Tiwari ,  Steven L. Wright

IPC: H01L31/0224 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/022408 ,  H01L31/105 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

Abstract: A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.

Abstract translation: 公开了具有相反导电类型的自对准梯度接触扩散区域的侧向注入组III-V异质结构器件和制造这种器件的方法。 该器件包括由较低带隙III-V化合物半导体上形成的较高带隙III-V化合物半导体形成的异质结。 本发明的方法允许相反的导电型扩散区域同时扩散并穿透异质结。 这导致在扩散区域中形成异质结的化合物半导体材料的组成混合。

公开(公告)号：US4593307A

公开(公告)日：1986-06-03

申请号：US509732

申请日：1983-06-30

Applicant: Hans S. Rupprecht ,  Sandip Tiwari

Inventor： Hans S. Rupprecht ,  Sandip Tiwari

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45 ,  H01L23/48

CPC classification number: H01L21/28575 ,  H01L29/452 ,  Y10S148/084 ,  Y10S148/14

Abstract: This invention relates generally to ohmic contacts to substrates made of III-V compounds and to a process for fabricating such contacts. More specifically, the invention is directed to a contact to gallium arsenide having a given level of n-type dopant therein, a region of the substrate doped with germanium and a layer of a germanide of a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum disposed on the substrate. Still more specifically, the invention relates to an ohmic contact to gallium arsenide which includes an interface region of germanium heavily doped with arsenic disposed between the region doped with germanium and the layer of germanide. The contact is formed by evaporating germanium and a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum on the surface of an n-type gallium arsenide substrate and sintering the substrate in a reducing atmosphere for a time and at a temperature sufficient to form the first-to-form germanide of the refractory metal. The resulting contact is stable, has a very low contact resistance and may be subjected to later high temperature processing steps without affecting its characteristics.

Abstract translation: 本发明一般涉及由III-V化合物制成的衬底的欧姆接触以及制造这种接触的方法。 更具体地，本发明涉及其中具有给定水平的n型掺杂剂的砷化镓的接触，掺杂有锗的衬底的区域和选自钼， 设置在基板上的钨和钽。 更具体地，本发明涉及对砷化镓的欧姆接触，其包括重掺杂砷的锗的界面区域，其设置在掺杂有锗的区域和锗化物层之间。 接触是通过在n型砷化镓衬底的表面上蒸发锗和选自钼，钨和钽的难熔金属形成的，并在还原气氛中烧结衬底一段时间并在足以 形成难熔金属的第一个到形式的锗化物。 所得到的接触是稳定的，具有非常低的接触电阻并且可以经受稍后的高温处理步骤而不影响其特性。

公开(公告)号：US08987701B2

公开(公告)日：2015-03-24

申请号：US13322379

申请日：2010-05-28

Applicant: Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

Inventor： Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

IPC: H01L47/00 ,  H01L29/68 ,  H01L29/51

CPC classification number: H01L29/685 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Abstract translation: 在一个实施例中，提出了一种方法，包括提供具有电极的半导体结构，其中所述提供包括提供相变材料区域，并且其中所述方法还包括赋予相变材料区域能量以引起相位的相变 过渡材料区域。 通过引起相变材料区域的相变，可以改变半导体结构的状态。 还提出了一种装置，其包括包括电极和相变材料区域的结构，其中该装置可操作以将能量传递给相变材料区域，以引起相变材料区域的相变而不发生相变 相变材料区域依赖于通过相变材料区域的电子传输。