公开(公告)号：US20120183825A1

公开(公告)日：2012-07-19

申请号：US13323109

申请日：2011-12-12

Applicant: Seung-Hun Lee ,  Sang-Ho Lee

Inventor： Seung-Hun Lee ,  Sang-Ho Lee

IPC: H01M10/36 ,  H01M10/0587 ,  H01M10/04

CPC classification number: H01M10/0431 ,  H01M2/021 ,  H01M2/0212 ,  H01M2/0275 ,  H01M10/04 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0565 ,  H01M10/0587 ,  H01M2004/025 ,  Y10T29/49108 ,  Y10T29/4911

Abstract: An embodiment is directed to a battery, including a housing, an electrode assembly in the housing, the electrode assembly including a first electrode member, a separator, and a second electrode member wound about a first axis, the first axis extending in a first direction, the electrode assembly having a thickness in a second direction orthogonal to the first direction and having a length in a third direction orthogonal to the first and second directions, the length being greater than the thickness, the electrode assembly having a curvature about a second axis that is parallel to the first axis, and first and second electrode tabs, the first electrode tab and the second electrode tab being connected to the first electrode member and the second electrode member, respectively, the first and second electrode tabs protruding from the electrode assembly in a direction orthogonal to the first direction.

Abstract translation: 一个实施例涉及一种电池，包括壳体，壳体中的电极组件，电极组件包括第一电极构件，隔板和围绕第一轴线缠绕的第二电极构件，第一轴线沿第一方向延伸 所述电极组件具有与所述第一方向正交的第二方向的厚度，并且具有与所述第一和第二方向正交的第三方向的长度，所述长度大于所述厚度，所述电极组件具有围绕第二轴线的曲率 平行于第一轴线的第一和第二电极接头以及第一和第二电极接头，第一电极接头和第二电极接头分别连接到第一电极部件和第二电极部件，从电极组件突出的第一和第二电极接头 在与第一方向正交的方向上。

公开(公告)号：US20120058609A1

公开(公告)日：2012-03-08

申请号：US13223783

申请日：2011-09-01

Applicant: Seung-Hun LEE ,  Byeong-Chan Lee ,  Sang-Bom Kang

Inventor： Seung-Hun LEE ,  Byeong-Chan Lee ,  Sang-Bom Kang

IPC: H01L21/8238 ,  H01L21/20

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

公开(公告)号：US20110266627A1

公开(公告)日：2011-11-03

申请号：US13096311

申请日：2011-04-28

Applicant: Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

Inventor： Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

IPC: H01L27/092 ,  H01L27/085

CPC classification number: H01L21/823481 ,  H01L21/823878

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas.

Abstract translation: 半导体器件包括半导体衬底，其包括由器件隔离层限定的多个有源区，与多个有源区交叉的栅极线结构，半导体衬底上的缓冲绝缘层，缓冲绝缘层接触一侧的一部分 栅极线结构，缓冲绝缘层上的接触蚀刻停止层以及通过缓冲绝缘层和接触蚀刻阻挡层的接触插塞，以连接到多个有源区。

公开(公告)号：US20100001349A1

公开(公告)日：2010-01-07

申请号：US12495501

申请日：2009-06-30

Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC: H01L27/088

CPC classification number: H01L21/823425 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US06343036B1

公开(公告)日：2002-01-29

申请号：US09157271

申请日：1998-09-18

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C700

CPC classification number: G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5862087A

公开(公告)日：1999-01-19

申请号：US766562

申请日：1996-12-13

Applicant: Seung-Hun Lee

Inventor： Seung-Hun Lee

IPC: G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/84

Abstract: A redundancy circuit for activating redundant memory cells when a semiconductor memory device is found to have defective memory cells, which redundancy circuit comprises, in order to overcome the problems of an address reset and a precharging of the first node which determines the redundancy addressing output signal of the redundancy circuit, additional switching circuit which is controlled by a clock signal of the memory device being made to be connected between a ground node and a switching circuit connected to a plurality of fuses, and a precharging circuit for precharging the first node to a high voltage level being made to also controlled by the clock signal.

Abstract translation: 当发现半导体存储器件具有缺陷存储器单元时，冗余电路包括冗余电路，用于激活冗余存储器单元，以便克服确定冗余寻址输出信号的地址复位和预充电的问题 由连接在接地节点和连接到多个保险丝的开关电路之间的存储器件的时钟信号控制的附加开关电路以及用于将第一节点预充电到预充电电路的预充电电路 高压电平也由时钟信号控制。

公开(公告)号：US5610869A

公开(公告)日：1997-03-11

申请号：US511815

申请日：1995-08-07

Applicant: Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

Inventor： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC: G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract translation: 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

公开(公告)号：US09818824B2

公开(公告)日：2017-11-14

申请号：US14968049

申请日：2015-12-14

Applicant: Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

IPC: H01L29/161 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L29/161 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

公开(公告)号：US20160104775A1

公开(公告)日：2016-04-14

申请号：US14826174

申请日：2015-08-13

Applicant: JONGRYEOL YOO ,  HYUN JUNG LEE ,  SUNJUNG KIM ,  SEUNG HUN LEE ,  Eunhye CHOI

Inventor： JONGRYEOL YOO ,  HYUN JUNG LEE ,  SUNJUNG KIM ,  SEUNG HUN LEE ,  Eunhye CHOI

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/165 ,  H01L27/088

CPC classification number: H01L29/1054 ,  H01L21/823412 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient.

Abstract translation: 半导体器件包括在半导体衬底上的包括第一和第二区域的缓冲层，第一区域的缓冲层上的第一沟道层，第二区域的缓冲层上的第二沟道层以及第二区域之间的间隔层 通道层和缓冲层。 缓冲层，第一和第二沟道层以及间隔层由包括锗的半导体材料形成。 第一和第二沟道层之间的锗浓度差大于缓冲层和第二沟道层之间的锗浓度差。 间隔层具有锗浓度梯度。

公开(公告)号：US09108389B2

公开(公告)日：2015-08-18

申请号：US13979312

申请日：2012-01-11

Applicant: Dong Sik Jang ,  Seung Hun Lee

Inventor： Dong Sik Jang ,  Seung Hun Lee

IPC: B41M5/382 ,  B32B15/04 ,  B44C1/17

CPC classification number: B32B15/04 ,  B41M5/38214 ,  B41M2205/30 ,  B41M2205/38 ,  B44C1/1704 ,  B44C1/1712 ,  B44C1/1716 ,  B44C1/1729 ,  Y10T428/24851

Abstract: Disclosed is a transfer film which is transferred to an injection molding product. The transfer film includes a protective layer a printing layer which is stacked on the protective layer; a metal deposition layer which is deposited on the printing layer so as to have an island structure and thus to provide non-conductive property; and adhesive layer which is deposited on the metal deposition layer, thereby providing metal color and non-conductive property.

Abstract translation: 公开了转移到注射成型产品的转移膜。 转印膜包括保护层，层叠在保护层上的印刷层; 金属沉积层，其沉积在印刷层上以具有岛状结构，从而提供非导电性; 以及沉积在金属沉积层上的粘合剂层，从而提供金属颜色和非导电性。