公开(公告)号：US07985603B2

公开(公告)日：2011-07-26

申请号：US12025207

申请日：2008-02-04

Applicant: Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

Inventor： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract translation: 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

公开(公告)号：US07514734B2

公开(公告)日：2009-04-07

申请号：US11220292

申请日：2005-09-06

Applicant: Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

Inventor： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

IPC: H01L29/76

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract translation: 硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

公开(公告)号：US20080081380A1

公开(公告)日：2008-04-03

申请号：US11706722

申请日：2007-02-15

Applicant: Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L21/00

CPC classification number: H01L28/75 ,  H01L27/11507 ,  H01L28/55

Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Abstract translation: 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

公开(公告)号：US07220600B2

公开(公告)日：2007-05-22

申请号：US11016400

申请日：2004-12-17

Applicant: Scott R. Summerfelt ,  Lindsey H. Hall ,  Kezhakkedath R. Udayakumar ,  Theodore S. Moise, IV

Inventor： Scott R. Summerfelt ,  Lindsey H. Hall ,  Kezhakkedath R. Udayakumar ,  Theodore S. Moise, IV

IPC: H01G7/06 ,  H01L32/00

CPC classification number: H01L21/0206 ,  H01L21/02071 ,  H01L28/55 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75

Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Abstract translation: 提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。 所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。 所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化处理之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205） 在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

公开(公告)号：US06984857B2

公开(公告)日：2006-01-10

申请号：US10620516

申请日：2003-07-16

Applicant: K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Jeff L. Large

Inventor： K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Jeff L. Large

IPC: H01L29/76

CPC classification number: H01L28/57 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract translation: 提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。 氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

公开(公告)号：US06902939B2

公开(公告)日：2005-06-07

申请号：US10223643

申请日：2002-08-19

Applicant: Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

Inventor： Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract translation: 在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

公开(公告)号：US06876021B2

公开(公告)日：2005-04-05

申请号：US10303560

申请日：2002-11-25

Applicant: J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

Inventor： J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Abstract translation: 本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。 本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。 通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

公开(公告)号：US06828161B2

公开(公告)日：2004-12-07

申请号：US10313068

申请日：2002-12-06

Applicant: Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

Inventor： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract translation: 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

公开(公告)号：US06773930B2

公开(公告)日：2004-08-10

申请号：US10305838

申请日：2002-11-26

Applicant: Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

Inventor： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Tomojuki Sakoda ,  Chiu Chi ,  Theodore S. Moise, IV

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/75

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.

Abstract translation: 本发明涉及一种形成FeRAM集成电路的方法，其包括在FeRAM电容器堆叠中形成底部电极层之前形成TiAlON底部电极扩散阻挡层。 随后，当执行电容器堆叠蚀刻时，TiAlON扩散阻挡层中未被FeRAM电容器堆叠覆盖的部分被TiAlON扩散阻挡层内的氧基本上各向异性地蚀刻，基本上防止了其横向蚀刻。 以上述方式，防止了FeRAM电容器堆叠下的TiAlON扩散阻挡层的底切。 在本发明的另一方面，形成FeRAM电容器的方法包括形成多层底电极扩散阻挡层。 这种形成包括在层间电介质层和导电接触面上形成TiN层，并在其上形成扩散阻挡层。 TiN层至少部分地填充存在于导电接触中的任何接缝，从而提高了FeRAM电容器和层间电介质中的导电接触之间的导电性。

公开(公告)号：US06660612B1

公开(公告)日：2003-12-09

申请号：US10289606

申请日：2002-11-07

Applicant: Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

Inventor： Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

IPC: H01L2176

CPC classification number: H01L27/11502 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/11507 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.

Abstract translation: 本发明的一个方面涉及一种半导体器件的制造方法，其中通过多个相邻的填充沟槽形成对准标记。 处理工具检测沟槽，好像它们是较大尺寸的单个填充沟槽。 当沟槽被金属填充时，与当金属形成单个大沟槽时相比，金属更容易被保护以免氧化，这是当沟槽被钨填充时的效果。 本发明的另一方面涉及由多个填充钨的沟槽形成的对准标记。 对准标记可用于将FeRAM电容器堆叠的图案对准下层钨触点。