公开(公告)号：US06940741B2

公开(公告)日：2005-09-06

申请号：US10807272

申请日：2004-03-24

申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115 ,  G11C11/24

CPC分类号： H01L27/11502 ,  G11C8/14 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  H01L27/10805

摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

公开(公告)号：US20050016636A1

公开(公告)日：2005-01-27

申请号：US10493639

申请日：2002-05-10

申请人： Yutaka Kobayashi ,  Toshihiko Taniuchi ,  Yoshikuni Nakao

发明人： Yutaka Kobayashi ,  Toshihiko Taniuchi ,  Yoshikuni Nakao

IPC分类号： C22C38/00 ,  C22C38/06 ,  C22C38/44

CPC分类号： C22C38/02 ,  C22C38/001 ,  C22C38/002 ,  C22C38/004 ,  C22C38/04 ,  C22C38/06 ,  C22C38/44

摘要： The present invention provides a stainless steel which is suitable for use in the food manufacturing plant, particularly a soy sauce manufacturing plant. A stainless steel to be used in the environment which contains organic acid and common salt comprising, C; 0.05 wt % or less, Si; 1.00 wt % or less, Mn; 1.00 wt % or less, P; 0.040 wt % or less, S; 0.03 wt % or less, Ni; 40.0 wt % or less, 16.0 wt %≦Cr≦26.0 wt %, 2.0 wt %≦Mo≦8.0 wt %, 0.05 wt %≦Al≦0.100 wt %, 0.10 wt %≦N≦0.30 wt %, Mg: 0.005 wt % or less, Ca; 0.0010 wt % or less and balance consisting of Fe and inevitable impurities, and satisfying equation (1), Cr+3.3Mo+20N≧38   (1) wherein, Cr, Mo and N show the content of each ingredients by weight %.

摘要翻译： 本发明提供一种适用于食品制造厂，特别是酱油制造厂的不锈钢。 用于环境中的含有有机酸和常盐的不锈钢，包括C; 0.05重量％以下，Si： 1.00重量％以下，Mn： 1.00重量％以下，P： 0.040重量％以下，S： 0.03重量％以下，Ni： 40.0重量％或更少，16.0重量％<= Cr <= 26.0重量％，2.0重量％<= Mo <= 8.0重量％，0.05重量％<= Al <= 0.100重量％，0.10重量％ 0.30重量％，Mg：0.005重量％以下，Ca： 0.0010重量％以下，余量由Fe和不可避免的杂质组成，满足式（1），Cr + 3.3Mo + 20N> = 38（1）其中，Cr，Mo和N分别表示各成分的重量％。

公开(公告)号：US20050016389A1

公开(公告)日：2005-01-27

申请号：US10604501

申请日：2003-07-25

申请人： Yutaka Kobayashi

发明人： Yutaka Kobayashi

IPC分类号： A23L1/00 ,  A23P1/08 ,  A23P1/00

CPC分类号： A23P20/20

摘要： The present invention and method relates to an apparatus for forming and separating rolled sushi dishes. The device comprises a non-stick, flexible mat with slots to facilitate the cutting of the rolled food product. The slots are positioned perpendicular to the axis of flexibility of the mat so that the formed food product may be cut into cylindrical portions.

摘要翻译： 本发明和方法涉及一种用于形成和分离轧制寿司盘的设备。 该装置包括具有槽的不粘的柔性垫，以便于切割滚动的食品。 槽垂直于垫子的柔性轴定位，使得成形的食品可以被切割成圆柱形部分。

公开(公告)号：US06740958B2

公开(公告)日：2004-05-25

申请号：US10115101

申请日：2002-04-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5828100A

公开(公告)日：1998-10-27

申请号：US714603

申请日：1996-09-16

申请人： Akihiko Tamba ,  Yutaka Kobayashi

发明人： Akihiko Tamba ,  Yutaka Kobayashi

IPC分类号： H01L29/78 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H02M7/537 ,  H01L27/02 ,  H01L29/74

CPC分类号： H01L29/1095 ,  H01L29/7397

摘要： An insulated gate semiconductor device has a semiconductor substrate having an irregular surface of raised portions and depressed portions, and a main device region and a protective circuit region. The protective circuit region is formed in a raised portion of the semiconductor substrate and includes a semiconductor device which is driven by an insulated gate electrode formed in a depressed portion of the semiconductor substrate. The raised portions and the depressed portions of the semiconductor substrate are formed by a trench etching method.

摘要翻译： 绝缘栅半导体器件具有半导体衬底，其具有凸起部分和凹陷部分的不规则表面，以及主器件区域和保护电路区域。 保护电路区域形成在半导体衬底的凸起部分中，并且包括由形成在半导体衬底的凹陷部分中的绝缘栅电极驱动的半导体器件。 半导体衬底的凸起部分和凹陷部分通过沟槽蚀刻方法形成。

公开(公告)号：US5787043A

公开(公告)日：1998-07-28

申请号：US394765

申请日：1995-02-27

申请人： Takashi Akioka ,  Yuji Yokoyama ,  Atsushi Hiraishi ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Koichi Motohashi

发明人： Takashi Akioka ,  Yuji Yokoyama ,  Atsushi Hiraishi ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Koichi Motohashi

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/844

摘要： A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.

摘要翻译： 提供了一种半导体器件，其包括通过将存储器分成多个块形成的存储器衬垫和布置在每个存储器块块处的电路布置，用于至少对该块内的缺陷存储器单元产生访问抑制信号。 使用这种布置，增加了用于消除缺陷的冗余存储单元阵列的访问速度，从而获得能够进行高速操作的半导体存储器件。

公开(公告)号：US5734188A

公开(公告)日：1998-03-31

申请号：US674185

申请日：1996-07-01

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L27/105 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/119

CPC分类号： H01L27/105

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

公开(公告)号：US5675548A

公开(公告)日：1997-10-07

申请号：US608605

申请日：1996-02-29

申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

公开(公告)号：US5663659A

公开(公告)日：1997-09-02

申请号：US488441

申请日：1995-06-07

申请人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

发明人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

IPC分类号： H01L27/06 ,  H03K19/013 ,  H03K19/01

CPC分类号： H01L27/0623 ,  H03K19/0136

摘要： The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form. This type of arrangement is used to effect a BiNMOS type of logic (inverter) circuit. In accordance with another structural scheme, in place of the first CMOS logic gate, a BiCMOS type of arrangement is effected in combination with the second CMOS logic gate and differentiator.

摘要翻译： 半导体IC器件具有由具有输入和输出端子的第一CMOS逻辑门和与第一CMOS逻辑门执行相同逻辑运算的第二CMOS逻辑门构成的电路装置，该第二CMOS逻辑门的输入端连接到 第一个CMOS逻辑门的输入端。 该装置还需要一个其输入端连接到第二CMOS逻辑门的输出端并具有连接到第一CMOS逻辑门的输出端的输出端的微分电路。 通过这样的布置，有效栅极传播延迟时间对输出负载的依赖性降低。 结果，因此，可以在确保高操作速度以及低功耗的同时，使用低电源电压来实现该配置。 CMOS逻辑门也可以与以射极跟随器电路形式连接的NPN双极晶体管结合起来。 这种类型的布置用于实现BiNMOS类型的逻辑（逆变器）电路。 根据另一结构方案，代替第一CMOS逻辑门，与第二CMOS逻辑门和微分器结合实现BiCMOS类型的布置。

公开(公告)号：US5614848A

公开(公告)日：1997-03-25

申请号：US482570

申请日：1995-06-07

申请人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

发明人： Yasuo Kaminaga ,  Yoji Nishio ,  Akihiro Tamba ,  Yutaka Kobayashi ,  Masataka Minami

IPC分类号： H01L27/06 ,  H03K19/013 ,  H03K19/01

CPC分类号： H01L27/0623 ,  H03K19/0136

摘要： The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

摘要翻译： 半导体IC器件具有这样的电路结构，其中一个或多个电路，例如在单个衬底上，包括由互补MOS电路的布置驱动的双极晶体管的图腾柱串联连接， 实现速度逻辑/切换操作。 还可以实现电路的布置，其中图腾柱串联连接由在电源端侧的PNP晶体管，以及在其接地或下拉侧上的NPN或NMOS晶体管构成。 通过这样的配置，可以在低工作电压下的输出信号摆幅最大化，同时实现相同的传播延迟时间和低功耗。 该装置还可以通过使用电容自举效应的电路以及IIL（I2L）设计方案来实现。