公开(公告)号：US08775694B2

公开(公告)日：2014-07-08

申请号：US13624644

申请日：2012-09-21

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Romain Oddoart ,  Cedric Favier

IPC: G06F13/28 ,  G06F3/05

CPC classification number: G06F13/28 ,  H03M1/1215 ,  Y02D10/14

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract translation: 一种设备包括中央处理单元（CPU）和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器（ADC）的模拟 - 数字转换器控制器（ADC控制器）。 另外，该设备还包括直接存储器存取系统（DMA系统），其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作，而无需CPU干预，以控制由ADC执行的转换操作 。

公开(公告)号：US20140089714A1

公开(公告)日：2014-03-27

申请号：US13786042

申请日：2013-03-05

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Ronan Barzic ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau ,  Morten Werner Lund

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system.

Abstract translation: 微控制器系统被组织成电源域。 微控制器系统的电源管理器可以响应于来自事件生成模块的事件而改变功率域的功率配置，而不激活微控制器系统的处理器。

公开(公告)号：US10783279B2

公开(公告)日：2020-09-22

申请号：US15679134

申请日：2017-08-16

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Martin Olsson ,  Arne Aas

IPC: G06F21/72 ,  H04L9/06

Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.

公开(公告)号：US10204057B2

公开(公告)日：2019-02-12

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/02 ,  G06F3/06

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

公开(公告)号：US20180024781A1

公开(公告)日：2018-01-25

申请号：US15385810

申请日：2016-12-20

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Ian Fullerton ,  Joseph Martinez ,  Martin Olsson

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/062 ,  G06F3/0655 ,  G06F12/0246 ,  G06F2212/1052 ,  G06F2212/72 ,  G06F2212/7201

Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

公开(公告)号：US09715601B2

公开(公告)日：2017-07-25

申请号：US14698330

申请日：2015-04-28

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen

IPC: G06F21/31 ,  G06F21/85 ,  G06F21/57 ,  G06F21/74

CPC classification number: G06F21/85 ,  G06F21/575 ,  G06F21/74

Abstract: Systems, methods and computer-readable mediums are disclosed for providing secure access in a microcontroller system. In some implementations, a microcontroller system comprises a system bus and a secure central processing unit (CPU) coupled to the system bus. The secure CPU is configured to provide secure access to the system bus. A non-secure CPU is also coupled to the system bus and is configured to provide non-secure access to the system bus. A non-secure memory is coupled to the system bus and is configured to allow the secure CPU and the non-secure CPU to exchange data and communicate with each other. A peripheral access controller (PAC) is coupled to the system bus and configured to enable secure access to a peripheral by the secure CPU while disabling non-secure access to the peripheral based upon a non-secure state of the non-secure CPU.

公开(公告)号：US09612983B2

公开(公告)日：2017-04-04

申请号：US13964971

申请日：2013-08-12

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Thierry Delalande ,  Ivar Holand ,  Mona Opsahl

IPC: G06F13/14 ,  G06F13/362 ,  G06F13/10

CPC classification number: G06F13/362 ,  G06F13/102 ,  G06F13/14

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

公开(公告)号：US09552385B2

公开(公告)日：2017-01-24

申请号：US13965020

申请日：2013-08-12

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F11/00

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

公开(公告)号：US09405720B2

公开(公告)日：2016-08-02

申请号：US13941671

申请日：2013-07-15

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US09257969B2

公开(公告)日：2016-02-09

申请号：US13632738

申请日：2012-10-01

Applicant: Atmel Corporation

Inventor： Tor Erik Leistad ,  Frode Milch Pedersen ,  Fredrik Larsen

IPC: H03L7/06 ,  H03K3/03 ,  H03K3/011 ,  H03L7/099 ,  H03L7/183 ,  H03K5/14 ,  H03L7/081

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/0997 ,  H03L7/183

Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract translation: 单独选择的延迟元件的延迟线可以作为开环模式的振荡器工作，以跟踪过程变化或驱动随着系统中的温度和电压而变化的时钟信号。 延迟线振荡器还可以在闭环模式下操作以匹配由调谐器比率给定的频率和参考时钟。 延迟线也可用于测量时钟抖动或占空比。