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公开(公告)号：US20120161255A1
公开(公告)日：2012-06-28
申请号：US12979592
申请日：2010-12-28
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： Embodiments of the invention provide methods of sealing a micro electromechanical systems (MEMS) cavity and devices resulting therefrom. A first aspect of the invention provides a method of sealing a micro electromechanical systems (MEMS) cavity in a substrate, the method comprising: forming in a substrate a cavity filled with a sacrificial material; forming a lid over the cavity; forming at least one vent hole over the lid extending to the cavity; removing the sacrificial material from the cavity; depositing a first material onto the lid such that a size of at least one vent hole at a surface of the substrate is reduced but not sealed; and depositing a second material onto the first material to seal the at least one vent hole, wherein a MEMS cavity within the substrate and beneath the at least one vent hole substantially retains a pressure at which the at least one vent hole is sealed by the second material.
摘要翻译： 本发明的实施例提供了密封微机电系统（MEMS）腔和由此产生的装置的方法。 本发明的第一方面提供了一种密封衬底中的微机电系统（MEMS）空腔的方法，所述方法包括：在衬底中形成填充有牺牲材料的腔体; 在空腔上形成盖子; 在所述盖上形成延伸到所述空腔的至少一个通气孔; 从腔中去除牺牲材料; 将第一材料沉积到所述盖上，使得所述基板的表面处的至少一个通气孔的尺寸减小但不被密封; 以及将第二材料沉积到所述第一材料上以密封所述至少一个通气孔，其中所述基底内的MEMS空腔和所述至少一个通气孔下方基本上保持所述至少一个通气孔被所述第二通气孔密封的压力 材料。
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22.发明申请公开(公告)号：US20120151748A1
公开(公告)日：2012-06-21
申请号：US13404485
申请日：2012-02-24
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.
摘要翻译： 公开的实施例包括设计电感器的方法。 电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。
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公开(公告)号：US20120133006A1
公开(公告)日：2012-05-31
申请号：US12955220
申请日：2010-11-29
IPC分类号： H01L29/84
CPC分类号： H01G5/18 , B81B3/0072 , B81B2203/0118 , B81C2201/0167 , H01G5/16
摘要： In one embodiment, a semiconductor structure includes a beam positioned within a sealed cavity, the beam including: an upper insulator layer including one or more layers; and a lower insulator layer including one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer, such that the beam bends.
摘要翻译： 在一个实施例中，半导体结构包括位于密封空腔内的光束，所述光束包括：包括一层或多层的上绝缘体层; 以及包括一层或多层的下绝缘体层，其中上绝缘体层的复合应力不同于下绝缘体层的复合应力，使得光束弯曲。
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公开(公告)号：US20120115303A1
公开(公告)日：2012-05-10
申请号：US13354371
申请日：2012-01-20
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。
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公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。
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公开(公告)号：US20120042714A1
公开(公告)日：2012-02-23
申请号：US12858961
申请日：2010-08-18
申请人： Anthony K. Stamper
发明人： Anthony K. Stamper
IPC分类号： G01M3/04
摘要： A hermeticity sensor for a device includes a beam positioned within a substantially hermetically sealed cavity. The beam includes a stress that changes in response to being exposed to ambient from outside the cavity. A related method is also provided.
摘要翻译： 用于装置的气密传感器包括位于基本上密封的空腔内的梁。 梁包括响应于从外部暴露于环境的应力。 还提供了相关的方法。
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27.发明授权Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner 有权牺牲无机聚合物金属间介质大马士革丝和通孔衬里公开(公告)号：US08053901B2
公开(公告)日：2011-11-08
申请号：US12917154
申请日：2010-11-01
IPC分类号： H01L23/48
CPC分类号： H01L21/02167 , H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/312 , H01L21/3121 , H01L21/3122 , H01L21/3148 , H01L21/31612 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76831 , H01L21/76835 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.
摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，互连结构的通孔区域可以用包含SiO 2，SiCOH或掺杂的硅酸盐玻璃的机械刚性电介质来加强。
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公开(公告)号：US20110227225A1
公开(公告)日：2011-09-22
申请号：US13116622
申请日：2011-05-26
申请人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。
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29.发明申请METHODS FOR FORMING A BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM 有权形成包含冷却机构的粘合半导体基板的方法公开(公告)号：US20110201151A1
公开(公告)日：2011-08-18
申请号：US13038467
申请日：2011-03-02
IPC分类号： H01L21/60
CPC分类号： G06F17/5068 , H01L23/3672 , H01L23/473 , H01L23/481 , H01L25/0657 , H01L27/0688 , H01L2224/16 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/12044
摘要： Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.
摘要翻译： 将两个半导体衬底的底侧与其间的至少一个接合材料层接合在一起，并结合以形成键合衬底。 在所述至少一个接合层内设置有具有两个开口的腔体和它们之间的连续路径。 在键合衬底内形成至少一个通过衬底通孔和其它金属互连结构。 在该键合衬底中的半导体器件的操作期间，使用该空腔作为冷却通道，通过该冷却通道冷却流体以冷却接合的半导体衬底。 或者，在至少一个接合层内形成具有两个端部的导电冷却翅片和它们之间的连续路径。 导电冷却翅片的两个端部连接到散热器，以在键合衬底中的半导体器件的操作期间冷却接合的半导体衬底。
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公开(公告)号：US07968975B2
公开(公告)日：2011-06-28
申请号：US12188234
申请日：2008-08-08
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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