公开(公告)号：US20060189107A1

公开(公告)日：2006-08-24

申请号：US11402039

申请日：2006-04-11

Applicant: Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

Inventor： Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

IPC: H01L21/28

CPC classification number: H01L29/872 ,  H01L27/0814 ,  H01L29/0684 ,  H01L29/868

Abstract: Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.

Abstract translation: 合并的P-i-N肖特基器件，其中相反掺杂的扩散延伸到深度并且已经间隔开，使得该器件能够吸收与具有相对更深的相对掺杂的扩散区域的快速恢复外延二极管相当的反向雪崩能量。

公开(公告)号：US07091572B2

公开(公告)日：2006-08-15

申请号：US11233760

申请日：2005-09-23

Applicant: Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Rue Redda ,  Davide Chiola

Inventor： Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Rue Redda ,  Davide Chiola

IPC: H01L29/861 ,  H01L31/107

CPC classification number: H01L29/402 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/8611

Abstract: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

Abstract translation: 快速恢复二极管具有由终端区域包围的单个大面积P / N结。 与中心有源区接触的阳极触点在氧化物终止环的内周边延伸，并且EQR金属环在氧化物终止环的外周延伸。 铂原子扩散到器件的后表面。 描述三个掩模过程。 在四掩模工艺中添加非晶硅层，并且在五个掩模工艺中添加多个间隔保护环。

公开(公告)号：US20060017130A1

公开(公告)日：2006-01-26

申请号：US11233760

申请日：2005-09-23

Applicant: Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Rue Redda ,  Davide Chiola

Inventor： Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Rue Redda ,  Davide Chiola

IPC: H01L29/861 ,  H01L27/095 ,  H01L29/88

CPC classification number: H01L29/402 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/8611

Abstract: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

Abstract translation: 快速恢复二极管具有由终端区域包围的单个大面积P / N结。 与中心有源区接触的阳极触点在氧化物终止环的内周边延伸，并且EQR金属环在氧化物终止环的外周延伸。 铂原子扩散到器件的后表面。 描述三个掩模过程。 在四掩模工艺中添加非晶硅层，并且在五个掩模工艺中添加多个间隔保护环。

公开(公告)号：US20050230777A1

公开(公告)日：2005-10-20

申请号：US11073123

申请日：2005-03-04

Applicant: Davide Chiola ,  He Zhi ,  Kohji Andoh ,  Daniel Kinzer

Inventor： Davide Chiola ,  He Zhi ,  Kohji Andoh ,  Daniel Kinzer

IPC: H01L21/20 ,  H01L27/08 ,  H01L29/40 ,  H01L29/872 ,  H01L31/119

CPC classification number: H01L29/7811 ,  H01L27/08 ,  H01L27/0802 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/872

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract translation: 一种具有终端结构的半导体器件，其包括设置在螺旋沟槽内并连接在该器件的两个电源极之间的至少一个螺旋电阻器。

公开(公告)号：US06930371B2

公开(公告)日：2005-08-16

申请号：US10771559

申请日：2004-02-03

Applicant: Fabio Necco ,  Davide Chiola ,  Kohji Andoh

Inventor： Fabio Necco ,  Davide Chiola ,  Kohji Andoh

IPC: G01K7/01 ,  H01L27/02 ,  H01L29/868 ,  H01L29/872 ,  H01L31/058 ,  H01L33/00

CPC classification number: H01L29/868 ,  G01K7/01 ,  H01L27/0248 ,  H01L29/872 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A temperature-sensing diode has an anode and a cathode disposed on top and an isolated, metallization layer on bottom of a diode die. For example, the temperature-sensing diode is a Schottky diode without a guard ring and any passivation, making the temperature-sensing diode inexpensive to fabricate, easy to attach in close proximity to a heat-generating device and resistant to electronic noise from high power devices and stray electronic signals. The location of the anode and cathode on the same surface of the diode package provides for easy connection, such as by wire bonds, with an external circuit for providing a constant forward bias current and for amplification of the output voltage signal by an operational amplifier. The isolated, metallization layer provides for easy attachment of the temperature-sensing diode in close proximity to heat-generating power devices. A dielectric film isolates the temperature-sensing diode from the metallization layer and underlying substrate.

Abstract translation: 温度感测二极管具有设置在顶部的阳极和阴极以及在二极管管芯的底部上的隔离的金属化层。 例如，温度感测二极管是没有保护环和任何钝化的肖特基二极管，使得温度感测二极管制造成本低廉，易于附接到发热器件附近并且抵抗来自高功率的电子噪声 设备和杂散电子信号。 阳极和阴极在二极管封装的相同表面上的位置提供了容易的连接，例如通过引线键合，外部电路用于提供恒定的正向偏置电流和用于由运算放大器放大输出电压信号。 隔离的金属化层提供了容易地将温度感测二极管附接到发热功率器件附近。 电介质膜将温度感测二极管与金属化层和下面的衬底隔离。

公开(公告)号：US06927141B2

公开(公告)日：2005-08-09

申请号：US10642837

申请日：2003-08-18

Applicant: Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Ruo Redda ,  Davide Chiola

Inventor： Kohji Andoh ,  Silvestro Fimiani ,  Fabrizio Ruo Redda ,  Davide Chiola

IPC: H01L21/329 ,  H01L29/06 ,  H01L29/32 ,  H01L29/40 ,  H01L29/861 ,  H01L21/20

CPC classification number: H01L29/402 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/8611

Abstract: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

Abstract translation: 快速恢复二极管具有由终端区域包围的单个大面积P / N结。 与中心有源区接触的阳极触点在氧化物终止环的内周边延伸，并且EQR金属环在氧化物终止环的外周延伸。 铂原子扩散到器件的后表面。 描述三个掩模过程。 在四掩模工艺中添加非晶硅层，并且在五个掩模工艺中添加多个间隔保护环。

公开(公告)号：US20050161758A1

公开(公告)日：2005-07-28

申请号：US10766460

申请日：2004-01-27

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L21/329 ,  H01L21/763 ,  H01L27/08 ,  H01L27/095 ,  H01L29/06 ,  H01L29/872 ,  H01L21/00 ,  H01L29/47 ,  H01L29/812 ,  H01L29/861 ,  H01L31/07 ,  H01L31/107 ,  H01L31/108

CPC classification number: H01L29/8725 ,  H01L21/763 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/872

Abstract: A trench schottky diode which includes a thin insulation layer on the sidewalls of its trenches and a relatively thicker insulation layer at the bottoms of its trenches.

公开(公告)号：US20050124085A1

公开(公告)日：2005-06-09

申请号：US10728482

申请日：2003-12-04

Applicant: Kohji Andoh ,  Davide Chiola

Inventor： Kohji Andoh ,  Davide Chiola

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/20

Abstract: A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate.

Abstract translation: 一种用于调整半导体衬底的表面中的电阻率的方法，包括半导体衬底的主表面上的区域的选择性测量和反掺杂。

公开(公告)号：US08766430B2

公开(公告)日：2014-07-01

申请号：US13517654

申请日：2012-06-14

Applicant: Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

Inventor： Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

IPC: H01L23/48

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/11 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H05K1/0296 ,  H05K3/308 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract translation: 根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。 该模块还包括第二半导体器件和电路板。 第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。 电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。 在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

公开(公告)号：US08304305B2

公开(公告)日：2012-11-06

申请号：US13156037

申请日：2011-06-08

Applicant: Davide Chiola ,  Carsten Schaeffer

Inventor： Davide Chiola ,  Carsten Schaeffer

IPC: H01L21/8238

CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/66348

Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.

Abstract translation: 提出了半导体元件的制造方法。 该方法包括提供具有第一表面的半导体本体; 在所述第一表面上形成掩模，其中所述掩模具有用于限定沟槽的相应位置的开口; 使用掩模在半导体本体中产生沟槽，其中台面结构保留在相邻的沟槽之间; 使用掩模将第一导电类型的第一掺杂剂引入沟槽的底部; 进行第一热步骤; 将与第一导电类型互补的第二导电类型的第二掺杂剂至少引入到沟槽的底部; 并进行第二热步骤。