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公开(公告)号：US06924191B2
公开(公告)日：2005-08-02
申请号：US10463460
申请日：2003-06-16
IPC分类号： H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/8242
CPC分类号： H01L21/31122 , H01L21/0337 , H01L21/0338 , H01L21/28114 , H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.
摘要翻译： 一种在尺寸减小的基板上制造特征的方法。 特征通过在衬底的区域上限定第一掩模而形成。 第一个掩模使用光刻技术定义。 然后在第一掩模的一个或多个侧壁上顺应地形成第二掩模。 通过去除第一掩模在衬底上形成特征，然后使用第二掩模作为蚀刻掩模蚀刻衬底。
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公开(公告)号：US06852647B2
公开(公告)日：2005-02-08
申请号：US10383839
申请日：2003-03-07
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L21/3146 , H01L21/31633 , H01L21/3212 , H01L21/7681 , H01L21/76828 , H01L21/76829 , H01L21/7684
摘要： A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.
摘要翻译： 提供了一种用于处理衬底的方法，包括去除设置在低k电介质材料上的无定形碳材料，具有最小或减少的缺陷形成和低k电介质材料的最小介电常数变化。 在一个方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积至少一个电介质层，其中介电层包括硅，氧和碳，并且具有约3或更小的介电常数，形成无定形碳 在所述至少一个电介质层上的材料，以及通过将所述一个或多个非晶碳层暴露于含氢气体的等离子体来去除所述一个或多个非晶碳层。
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公开(公告)号：US06573030B1
公开(公告)日：2003-06-03
申请号：US09590322
申请日：2000-06-08
申请人： Kevin Fairbairn , Michael Rice , Timothy Weidman , Christopher S Ngai , Ian Scot Latchford , Christopher Dennis Bencher , Yuxiang May Wang
发明人： Kevin Fairbairn , Michael Rice , Timothy Weidman , Christopher S Ngai , Ian Scot Latchford , Christopher Dennis Bencher , Yuxiang May Wang
IPC分类号： G03F700
CPC分类号： H01L21/76829 , C23C16/26 , H01L21/0276 , H01L21/28035 , H01L21/3081 , H01L21/3088 , H01L21/31138 , H01L21/31144 , H01L21/3146 , H01L21/31612 , H01L21/32137 , H01L21/76802 , H01L21/76807
摘要： A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.
摘要翻译： 一种使用无定形碳膜形成集成电路的方法。 无定形碳膜通过热分解包含烃化合物和惰性气体的气体混合物而形成。 无定形碳膜与集成电路制造工艺兼容。 在一个集成电路制造工艺中，非晶碳膜用作硬掩模。 在另一个集成电路制造工艺中，无定形碳膜是用于深紫外（DUV）光刻的抗反射涂层（ARC）。 在又一集成电路制造工艺中，多层无定形碳抗反射涂层用于DUV光刻。
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公开(公告)号：US06541397B1
公开(公告)日：2003-04-01
申请号：US10112012
申请日：2002-03-29
IPC分类号： H01L2131
CPC分类号： H01L21/76826 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L21/3146 , H01L21/31633 , H01L21/3212 , H01L21/7681 , H01L21/76828 , H01L21/76829 , H01L21/7684
摘要： A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.
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公开(公告)号：US08357618B2
公开(公告)日：2013-01-22
申请号：US12257953
申请日：2008-10-24
IPC分类号： H01L21/31
CPC分类号： H01L21/3146 , H01L21/0337 , H01L21/0338
摘要： A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.
摘要翻译： 描述了使用光致抗蚀剂模板掩模使光刻工艺的频率加倍的方法。 首先提供其上形成有光致抗蚀剂层的器件层。 将光致抗蚀剂层图案化以形成光致抗蚀剂模板掩模。 在光致抗蚀剂模板掩模上沉积间隔物形成材料层。 蚀刻间隔物形成材料层以形成间隔物掩模并露出光刻胶模板掩模。 然后去除光刻胶模板掩模，并且最终将间隔掩模的图像转移到器件层。
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26.发明授权公开(公告)号：US08183150B2
公开(公告)日：2012-05-22
申请号：US12257806
申请日：2008-10-24
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , B08B7/0035 , C23C16/0245 , C23G5/00 , H01L21/02063 , H01L21/02068 , H01L21/02071 , H01L21/02074 , H01L21/31116 , H01L21/3148 , H01L21/3185 , H01L21/32136 , H01L21/76807 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.
摘要翻译： 本发明提供了通过原位等离子体还原方法形成的半导体器件，其在沉积其后的层之前，在相对低的温度下使用氮和氢（通常为氨）的化合物来还原氧化物或其它污染物。 与氧化物层的典型的物理溅射清洗工艺相比，这些层的粘合特性得到改善，氧的存在降低。 该方法对于双镶嵌结构的复杂要求尤其有用，特别是对于铜应用。
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27.发明授权Integral patterning of large features along with array using spacer mask patterning process flow 失效使用间隔物掩模图案化工艺流程的大型特征与阵列的整体图案化公开(公告)号：US07709396B2
公开(公告)日：2010-05-04
申请号：US12234101
申请日：2008-09-19
IPC分类号： H01L21/214 , H01L21/483
CPC分类号： H01L21/3086 , H01L21/3088 , Y10S438/95
摘要： Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.
摘要翻译： 本发明的实施例涉及在使用单个高分辨率光掩模的标准光刻处理技术的情况下与具有增加的密度（即减小的间距）的衬底上形成图案化特征的方法，同时还允许 图案化特征和图案化特征之间的间隔（沟槽宽度）在集成电路内变化。
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公开(公告)号：US20090111281A1
公开(公告)日：2009-04-30
申请号：US12257953
申请日：2008-10-24
IPC分类号： H01L21/31
CPC分类号： H01L21/3146 , H01L21/0337 , H01L21/0338
摘要： A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.
摘要翻译： 描述了使用光致抗蚀剂模板掩模使光刻工艺的频率加倍的方法。 首先提供其上形成有光致抗蚀剂层的器件层。 将光致抗蚀剂层图案化以形成光致抗蚀剂模板掩模。 在光致抗蚀剂模板掩模上沉积间隔物形成材料层。 蚀刻间隔物形成材料层以形成间隔物掩模并露出光刻胶模板掩模。 然后去除光刻胶模板掩模，并且最终将间隔掩模的图像转移到器件层。
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公开(公告)号：US20080026584A1
公开(公告)日：2008-01-31
申请号：US11492316
申请日：2006-07-25
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译： 使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。 通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。 为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。 可以定制退火以实现所需的蚀刻速率。
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公开(公告)号：US06946401B2
公开(公告)日：2005-09-20
申请号：US10655438
申请日：2003-09-04
IPC分类号： H01L21/302 , B08B7/00 , C23C16/02 , C23G5/00 , H01L21/02 , H01L21/306 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/314 , H01L21/318 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/10 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76834 , B08B7/0035 , C23C16/0245 , C23G5/00 , H01L21/02063 , H01L21/02068 , H01L21/02071 , H01L21/02074 , H01L21/31116 , H01L21/3148 , H01L21/3185 , H01L21/32136 , H01L21/76807 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.
摘要翻译： 本发明提供了一种原位等离子体还原方法以在沉积其后的层之前，在相对较低的温度下使用氮气和氢气（通常为氨）的化合物来还原氧化物或其它污染物。 与氧化物层的典型的物理溅射清洗工艺相比，这些层的粘合特性得到改善，氧的存在降低。 该方法对于双镶嵌结构的复杂要求尤其有用，特别是对于铜应用。
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