公开(公告)号：US20060071292A1

公开(公告)日：2006-04-06

申请号：US10711744

申请日：2004-10-01

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Alvin Joseph ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Alvin Joseph ,  Robert Rassel

IPC分类号： H01L29/93 ,  H01L31/108

CPC分类号： H01L29/66143 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/872

摘要： Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.

摘要翻译： 肖特基势垒二极管使用介电分离区域结合活性区域。 电介质分离区允许在至少一个维度上消除保护环。 此外，在集成电路器件的有源部分中使用介质分离区可以通过消除该保护环来减少或消除寄生电容。

公开(公告)号：US20070057343A1

公开(公告)日：2007-03-15

申请号：US11162471

申请日：2005-09-12

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L28/40

摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：US20060249848A1

公开(公告)日：2006-11-09

申请号：US10908346

申请日：2005-05-09

申请人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Daniel Edelstein ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： B32B7/12

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

公开(公告)号：US20060166454A1

公开(公告)日：2006-07-27

申请号：US10905940

申请日：2005-01-27

申请人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

发明人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/26513 ,  H01L27/0802 ,  H01L28/20

摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

摘要翻译： 提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。 在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。 激活可以通过沉积保护性介电层或单独的激活退火来进行。 在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

公开(公告)号：US20060152333A1

公开(公告)日：2006-07-13

申请号：US10905546

申请日：2005-01-10

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US20060046418A1

公开(公告)日：2006-03-02

申请号：US10711130

申请日：2004-08-26

申请人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/2652 ,  H01C17/26 ,  H01C17/265 ,  H01L28/20

摘要： A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

摘要翻译： 提供了在硅化后测量和调整电阻器的电阻值的电阻器的制造方法。 本发明的方法首先开始在半导体衬底的表面上提供具有电阻值的至少一个电阻器，例如多晶硅。 至少一个电阻器已进行硅化处理。 接下来，测量至少一个电阻器的电阻值，以确定硅化后电阻器的实际电阻。 在测量步骤之后，调整电阻器的电阻以获得所需的电阻值。 调整可以包括后硅化快速热退火和/或后硅化离子注入和低温快速热退火步骤。

公开(公告)号：US20070096260A1

公开(公告)日：2007-05-03

申请号：US11163741

申请日：2005-10-28

申请人： Ebenezer Eshun ,  Robert Rassel

发明人： Ebenezer Eshun ,  Robert Rassel

IPC分类号： H01L27/082

CPC分类号： H01L27/0802 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a device includes forming a dielectric layer on a substrate and forming a resistor on the dielectric layer. A second dielectric layer formed over the resistor is etched to expose edge portions of the resistor. The edge portions of the resistor are doped through the openings. A contact is formed in the openings. A device is also provided.

摘要翻译： 一种制造器件的方法包括在衬底上形成电介质层并在电介质层上形成电阻器。 形成在电阻器上方的第二介电层被蚀刻以暴露电阻器的边缘部分。 电阻器的边缘部分通过开口掺杂。 在开口中形成接触。 还提供了一种设备。

公开(公告)号：US20070241421A1

公开(公告)日：2007-10-18

申请号：US11279934

申请日：2006-04-17

申请人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

发明人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

IPC分类号： H01L21/331 ,  H01L29/00

CPC分类号： H01L29/7322 ,  H01L27/0921 ,  H01L29/0821 ,  H01L29/66272

摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

摘要翻译： 一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。 该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。 至少一个通孔电连接深子集电极和近子集电极。 该方法包括形成合并三阱双外延/双子集电极。

公开(公告)号：US20070029587A1

公开(公告)日：2007-02-08

申请号：US11161533

申请日：2005-08-08

申请人： Heidi Greer ,  Seong-Dong Kim ,  Robert Rassel ,  Kunal Vaed

发明人： Heidi Greer ,  Seong-Dong Kim ,  Robert Rassel ,  Kunal Vaed

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L29/93 ,  H01L27/0811 ,  H01L29/36 ,  H01L29/94

摘要： A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

摘要翻译： 形成MOS变容二极管，其栅极电极包括至少两个彼此短接的邻接的相对掺杂区域，其中两个区域与用于第一和第二类型晶体管的源极/漏极注入同时注入; 与第一类型的晶体管的源极/漏极注入同时形成与下部电极的至少一个接触; 变容二极管与栅绝缘体同时形成一种晶体管; 并且下电极与用于第一类型晶体管的阱同时形成，使得不需要附加掩模。