公开(公告)号：US08343815B2

公开(公告)日：2013-01-01

申请号：US12777881

申请日：2010-05-11

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/72

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

公开(公告)号：US20120286242A1

公开(公告)日：2012-11-15

申请号：US13556300

申请日：2012-07-24

申请人： Sarunya Bangsaruntip ,  Stephen J. Koester ,  Amlan Majumdar ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Stephen J. Koester ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC分类号： H01L29/775 ,  B82Y99/00

CPC分类号： H01L21/047 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/7391

摘要： A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion.

摘要翻译： 纳米线隧道器件包括通过第一焊盘区域和第二焊盘区域悬置在半导体衬底上方的纳米线，所述纳米线具有由围绕纳米线周向设置的栅极结构围绕的沟道部分，n型掺杂区域，包括第一部分 和与沟道部分相邻的纳米线的第二部分的p型掺杂区域。

公开(公告)号：US20120175678A1

公开(公告)日：2012-07-12

申请号：US13425654

申请日：2012-03-21

申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

摘要翻译： 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。

公开(公告)号：US08030145B2

公开(公告)日：2011-10-04

申请号：US12684225

申请日：2010-01-08

申请人： Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

发明人： Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

IPC分类号： H01L21/84

CPC分类号： H01L21/2652 ,  G03F9/7084 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/26553 ,  H01L21/2658 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/78648 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/8013 ,  H01L2224/802 ,  H01L2924/01019 ,  H01L2924/12044 ,  H01L2924/13091

摘要： A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.

摘要翻译： 完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。 背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。 在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。 全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

公开(公告)号：US20110062520A1

公开(公告)日：2011-03-17

申请号：US12949696

申请日：2010-11-18

申请人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/786

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US20100187607A1

公开(公告)日：2010-07-29

申请号：US12751302

申请日：2010-03-31

申请人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

发明人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L29/78648

摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

摘要翻译： 用于制造集成电路器件的半导体晶片结构包括体基片; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在所述下绝缘层上的导电层，所述导电层还具有形成在其中的一个或多个浅沟槽隔离（STI）区域; 形成在所述导电层和所述一个或多个STI区域上的蚀刻停止层; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。 还公开了随后的有源面积电平STI方案，结合半导体层上的前栅极形成。

公开(公告)号：US07601569B2

公开(公告)日：2009-10-13

申请号：US11761568

申请日：2007-06-12

申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

IPC分类号： H01L21/335 ,  H01L21/00 ,  H01L21/338 ,  H01L21/8234

CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

公开(公告)号：US20090218603A1

公开(公告)日：2009-09-03

申请号：US12463309

申请日：2009-05-08

申请人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

发明人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L29/04

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 描述了半导体膜的图案化方法。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US07427541B2

公开(公告)日：2008-09-23

申请号：US11638333

申请日：2006-12-12

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/76

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

摘要翻译： 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20070128820A1

公开(公告)日：2007-06-07

申请号：US11294730

申请日：2005-12-05

申请人： Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Robert Chau ,  Jack Kavalieros

发明人： Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Robert Chau ,  Jack Kavalieros

IPC分类号： H01L21/331

CPC分类号： H01L21/2652 ,  H01L29/1083 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method including introducing an implant of a dopant species into an active region of a device substrate, the dopant species comprising a conductivity type such that a conductivity of the implant is the same as a conductivity of a well of the active region wherein the introduction is aligned to junction regions of a device structure. An apparatus and system comprising an active device region of a substrate, the active device region comprising a well of a first conductivity, junction regions of a different second conductivity formed in the active region and separated by a channel and an implant of a dopant species in the well, the dopant species comprising a conductivity type such that a conductivity of the implant is the same as the first conductivity of the well and the implant is aligned to the junction regions.

摘要翻译： 一种方法，包括将掺杂剂物质的注入引入到器件衬底的有源区中，所述掺杂物种类包括导电类型，使得所述注入的导电性与所述有源区的阱的导电性相同，其中所述引入是 对准到器件结构的结区域。 一种包括衬底的有源器件区域的器件和系统，所述有源器件区域包括阱的第一导电性，形成在有源区中并由沟道形成的不同第二导电的结区域和掺杂物种类的注入 阱，包括导电类型的掺杂物种类，使得植入物的导电性与阱的第一导电性相同，并且注入物与连接区域对准。