公开(公告)号：US07102930B2

公开(公告)日：2006-09-05

申请号：US10944584

申请日：2004-09-16

申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Q. Nguyen ,  Sang Thanh Nguyen

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

公开(公告)号：US20050078526A1

公开(公告)日：2005-04-14

申请号：US10944584

申请日：2004-09-16

申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Ngoc Dang ,  Hung Nguyen ,  Sang Nguyen

IPC分类号： G11C16/12 ,  G11C11/34

CPC分类号： G11C16/12

摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

公开(公告)号：US20180158912A1

公开(公告)日：2018-06-07

申请号：US15724989

申请日：2016-04-27

申请人： Jin-woo HAN ,  Yuniarto WIDJAJA ,  Zvi OR-BACH ,  Dinesh MAHESHWARI ,  Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari

IPC分类号： H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  G11C16/10 ,  G11C16/26 ,  H01L27/24 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

公开(公告)号：US09087580B2

公开(公告)日：2015-07-21

申请号：US13244812

申请日：2011-09-26

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/14 ,  G11C11/404 ,  G11C11/56 ,  G11C13/00 ,  H01L27/108 ,  H01L27/24 ,  H01L29/78

CPC分类号： G11C14/0045 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/14 ,  G11C11/404 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/24 ,  H01L27/2445 ,  H01L27/2463 ,  H01L29/7841 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

摘要翻译： 提供半导体存储器，其中存储单元包括具有浮动体的无电容器晶体管，其被配置为当向单元施加电力时将数据作为电荷存储在其中。 电池还包括非易失性存储器，其包括电阻变化元件，电阻变化元件被配置为在多个预定条件中的任何一个下存储存储在浮动体中的数据。 描述了一种操作半导体存储器以用作易失性存储器的方法，同时当功率停止到半导体存储器时具有保留存储数据的能力。

公开(公告)号：US08767458B2

公开(公告)日：2014-07-01

申请号：US14046986

申请日：2013-10-06

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C8/10 ,  G11C8/16 ,  G11C11/40 ,  G11C11/403 ,  G11C11/405 ,  H01L27/1023 ,  H01L27/105 ,  H01Q1/2283

摘要： Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

摘要翻译： 多端口半导体存储器单元包括配置为被充电到指示存储器单元的存储器状态的电平的公共浮动体区域。 多端口半导体存储单元包括与所述浮体区域相接合的多个栅极和导电区域。 公开了用于制造存储器件的存储器单元阵列和操作所述存储器阵列的方法。

公开(公告)号：US20130292635A1

公开(公告)日：2013-11-07

申请号：US13937612

申请日：2013-07-09

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L27/105

CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US20120230123A1

公开(公告)日：2012-09-13

申请号：US13478014

申请日：2012-05-22

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C7/10 ,  G11C11/402 ,  G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7841 ,  H01L29/7881

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

摘要翻译： 提供了保持存储器单元的状态而不中断对存储单元的访问的方法，包括向单元施加反向偏置以将电荷泄漏偏离电池的浮动体，其中浮体的充电水平指示 记忆单元的状态; 并访问该单元格。

公开(公告)号：US08130547B2

公开(公告)日：2012-03-06

申请号：US12797334

申请日：2010-06-09

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7841 ,  H01L29/7881

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

摘要翻译： 提供了保持存储器单元的状态而不中断对存储单元的访问的方法，包括向单元施加反向偏置以将电荷泄漏偏离电池的浮动体，其中浮体的充电水平指示 记忆单元的状态; 并访问该单元格。

公开(公告)号：US08036033B2

公开(公告)日：2011-10-11

申请号：US12797164

申请日：2010-06-09

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C11/40 ,  G11C11/404 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在基板的第二位置处嵌入基板并具有第二导电类型，使得具有第一导电类型的基板的至少一部分位于第一和第二位置之间，并且用作浮体以存储 易失性存储器中的数据; 位于所述第一和第二位置之间且位于所述基板的表面之上并且通过绝缘层与所述表面绝缘的浮栅或捕获层; 浮动栅极或俘获层被配置为在中断对存储器单元的电力时，接收由易失性存储器存储的数据的传输并将数据作为非易失性存储器存储在浮动栅极或俘获层中; 以及位于浮置栅极或俘获层上方的控制栅极和位于浮置栅极或捕获层与控制栅极之间的第二绝缘层。

公开(公告)号：US08014200B2

公开(公告)日：2011-09-06

申请号：US12420659

申请日：2009-04-08

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C14/00

CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 所述捕获层包括第一和第二存储位置，其被配置为独立于彼此独立地存储作为非易失性存储器的数据; 以及位于捕获层上方的控制门。