公开(公告)号：US08987876B2

公开(公告)日：2015-03-24

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US20140264799A1

公开(公告)日：2014-09-18

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US10607957B2

公开(公告)日：2020-03-31

申请号：US15729889

申请日：2017-10-11

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US09534855B2

公开(公告)日：2017-01-03

申请号：US14549268

申请日：2014-11-20

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Kaustubh Ravindra Nagarkar ,  Matthew Jeremiah Misner ,  Faisal Razi Ahmad

IPC: F28F21/02 ,  F28F21/06

CPC classification number: F28F21/02 ,  B22F1/0018 ,  B22F3/11 ,  B22F3/1115 ,  B22F3/1137 ,  B22F3/114 ,  B22F3/24 ,  B22F7/00 ,  B22F7/02 ,  B22F2001/0037 ,  B22F2998/10 ,  F28F13/003 ,  F28F21/00 ,  F28F21/067 ,  F28F2255/18 ,  H01L23/3733 ,  Y10T428/249955 ,  Y10T428/249958 ,  Y10T428/249978 ,  B22F3/10 ,  B22F2003/244 ,  B22F3/26 ,  B22F2007/045

Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.

Abstract translation: 提供了复合泡沫，其包括设置在这种金属模板上的金属模板和保形原子级膜以形成3维互连结构。 金属模板包括具有多个第一非球形孔，多个第一非球形孔隙和第一表面积与体积比的多个烧结互连。 保形原子级膜具有多个第二非球形孔，第二非球形孔隙率和大约等于第一表面积体积比的第二表面积体积比。 多个烧结互连具有多个树枝状颗粒，并且共形原子尺度膜包括石墨烯层和六方氮化硼层中的至少一个。

公开(公告)号：US20150181763A1

公开(公告)日：2015-06-25

申请号：US14135678

申请日：2013-12-20

Applicant: General Electric Company

Inventor： Hendrik Pieter Jacobus de Bock ,  Stanton Earl Weaver, JR. ,  Tao Deng ,  Jay Todd Labhart ,  Pramod Chamarthy ,  Shakti Singh Chauhan ,  Graham Charles Kirk ,  Brian Patrick Hoden

IPC: H05K7/20 ,  B23P15/26 ,  H05K9/00

CPC classification number: B23P15/26 ,  B23P2700/09 ,  B23P2700/10 ,  F28D15/0266 ,  F28D15/0275 ,  H05K7/20681 ,  H05K9/0062 ,  Y10T29/49826

Abstract: An electronics chassis is provided. The electronics chassis includes a plurality of panels that define an interior space. One panel of the plurality of panels has a composite segment having an internal face and an external face. The electronics chassis further includes a conductive thermal pathway that extends through the panel from the internal face of the composite segment to the external face of the composite segment.

Abstract translation: 提供电子底盘。 电子机箱包括限定内部空间的多个面板。 所述多个面板中的一个面板具有具有内表面和外表面的复合区段。 电子底盘还包括导电热路径，其从复合段的内表面延伸穿过面板到复合段的外表面。

公开(公告)号：US20150090428A1

公开(公告)日：2015-04-02

申请号：US14041276

申请日：2013-09-30

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Joo Han Kim ,  William Harold King ,  Pramod Chamarthy ,  Tao Deng

IPC: F28D15/04 ,  B21D53/02

CPC classification number: F28D15/046 ,  Y10T29/49353

Abstract: A heat transfer device filled with a working fluid, includes a casing and a wick disposed within the casing. The wick includes a first sintered layer, a second sintered layer, and a third sintered layer. The first sintered layer is disposed proximate to an inner surface of the casing and the second sintered layer is disposed on the first sintered layer. The second sintered layer includes a first set of 3-dimensional sintered projections and a second set of 3-dimensional sintered projections disposed along a portion of the wick. Further, the third sintered layer is disposed on at least a portion of the second sintered layer. The heat transfer device includes at least one first sintered particle of the first sintered layer, which is smaller in size than at least one second pore of the second sintered layer.

Abstract translation: 填充有工作流体的传热装置包括壳体和设置在壳体内的芯。 芯包括第一烧结层，第二烧结层和第三烧结层。 第一烧结层设置在壳体的内表面附近，第二烧结层设置在第一烧结层上。 第二烧结层包括第一组三维烧结突起和沿着芯的一部分设置的第二组三维烧结突起。 此外，第三烧结层设置在第二烧结层的至少一部分上。 传热装置包括至少一个第一烧结层的第一烧结颗粒，其尺寸小于第二烧结层的至少一个第二孔。

公开(公告)号：US20150084207A1

公开(公告)日：2015-03-26

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/522 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US20150069612A1

公开(公告)日：2015-03-12

申请号：US14547667

申请日：2014-11-19

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/92144 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract translation: 公开了一种表面贴装封装结构，其提供了改善的热机械可靠性和更坚固的二级封装互连。 表面贴装封装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级金属互连结构以及电耦合到第一级的第二级I / O连接 互连并形成在与半导体器件相对的一侧的电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到多层衬底结构的第一表面，其中介电材料位于介电层和多层衬底结构之间以填充表面安装结构中的间隙，并提供 额外的结构完整性。

公开(公告)号：US20150060021A1

公开(公告)日：2015-03-05

申请号：US14018579

申请日：2013-09-05

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  William Harold King ,  Stanton Earl Weaver, JR. ,  Binoy Milan Shah ,  Tao Deng

IPC: F28D15/04 ,  B21D53/02

CPC classification number: F28D15/046 ,  B22F7/002 ,  B22F7/06 ,  B22F2999/00 ,  Y10T29/49353 ,  B22F3/02 ,  B22F2202/01

Abstract: A heat transfer device includes a casing and a wick disposed within the casing. The wick includes a first sintered layer and a second sintered layer. The first sintered layer includes a plurality of first sintered particles, having a first porosity and a plurality of first pores. The first sintered layer is disposed proximate to an inner surface of the casing. The second sintered layer includes a plurality of second sintered particles, having a second porosity and a plurality of second pores. The second sintered layer is disposed on the first sintered layer. The heat transfer device includes at least one first sintered particle smaller than at least one second pore and the first porosity is smaller than the second porosity.

Abstract translation: 传热装置包括壳体和设置在壳体内的芯。 芯包括第一烧结层和第二烧结层。 第一烧结层包括具有第一孔隙和多个第一孔的多个第一烧结颗粒。 第一烧结层设置在壳体的内表面附近。 第二烧结层包括具有第二孔隙率和多个第二孔隙的多个第二烧结颗粒。 第二烧结层设置在第一烧结层上。 传热装置包括至少一个小于至少一个第二孔的第一烧结颗粒，并且第一孔隙度小于第二孔隙率。

公开(公告)号：US20200185349A1

公开(公告)日：2020-06-11

申请号：US16788428

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/48 ,  H01L23/373 ,  H01L23/367 ,  H05K3/46 ,  H05K3/30 ,  H01L23/538 ,  H01L23/34

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.